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authorJohn Dykstra <john.dykstra1@gmail.com>2009-04-29 17:22:30 -0700
committerDavid S. Miller <davem@davemloft.net>2009-04-29 17:22:30 -0700
commitce105a082371570effb71541f299b1dc2771ee03 (patch)
treed352e8543adeb3392bb91ceb40301452f1aede0f
parentdd4d8ca6446538a904127838cb6c9a4cffe690f7 (diff)
pcnet32: Remove pointless memory barriers
These two memory barriers in performance-critical paths are not needed on x86. Even if some other architecture does buffer PCI I/O space writes, the existing memory-mapped I/O barriers are unlikely to be what is needed. Signed-off-by: John Dykstra <john.dykstra1@gmail.com> Acked-by: Don Fry <pcnet32@verizon.net> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/pcnet32.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
index e5e8c59243b6..1c35e1d637a0 100644
--- a/drivers/net/pcnet32.c
+++ b/drivers/net/pcnet32.c
@@ -1405,7 +1405,7 @@ static int pcnet32_poll(struct napi_struct *napi, int budget)
/* Set interrupt enable. */
lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
- mmiowb();
+
spin_unlock_irqrestore(&lp->lock, flags);
}
return work_done;
@@ -2597,7 +2597,7 @@ pcnet32_interrupt(int irq, void *dev_id)
val = lp->a.read_csr(ioaddr, CSR3);
val |= 0x5f00;
lp->a.write_csr(ioaddr, CSR3, val);
- mmiowb();
+
__napi_schedule(&lp->napi);
break;
}