summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJulie Zhu <julie.zhu@xilinx.com>2009-07-27 11:45:32 -0600
committerMichal Simek <monstr@monstr.eu>2009-09-22 08:50:14 +0200
commitafc26cb39e1e74c87a1b5eb013ead2590b91489c (patch)
tree4883ec8c0bb9b2b96c2894b573f8336e3c4396d4
parentd5b37092aae1edaa638b156b16d09854ad6a1ec0 (diff)
microblaze: Add architectural support for USB EHCI host controllers
Add architectural support for USB EHCI host controllers. It has been tested using the USB EHCI host controller from Xilinx Inc., using both High Speed devices and Full Speed devices. Signed-off-by: Julie Zhu <julie.zhu@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
-rw-r--r--arch/microblaze/Kconfig1
-rw-r--r--arch/microblaze/include/asm/io.h3
-rw-r--r--drivers/usb/Kconfig1
3 files changed, 4 insertions, 1 deletions
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 2db722d80d4d..bbd8327f1890 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -6,6 +6,7 @@ mainmenu "Linux/Microblaze Kernel Configuration"
config MICROBLAZE
def_bool y
select HAVE_LMB
+ select USB_ARCH_HAS_EHCI
select ARCH_WANT_OPTIONAL_GPIOLIB
config SWAP
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 7c3ec13b44d8..fc9997b73c09 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -210,6 +210,9 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
#define in_be32(a) __raw_readl((const void __iomem __force *)(a))
#define in_be16(a) __raw_readw(a)
+#define writel_be(v, a) out_be32((__force unsigned *)a, v)
+#define readl_be(a) in_be32((__force unsigned *)a)
+
/*
* Little endian
*/
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index dcd49f1e96d0..b35025ae4303 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -22,7 +22,6 @@ config USB_ARCH_HAS_HCD
default y if PCMCIA && !M32R # sl811_cs
default y if ARM # SL-811
default y if SUPERH # r8a66597-hcd
- default y if MICROBLAZE
default PCI
# many non-PCI SOC chips embed OHCI