arm: tegra: Use new platform types

This change is needed to support three different platforms, silicon,
 fpga and simulation.

Change-Id: I407853e1d86accbe3686deb4f34571fe6b10bcce
Reviewed-on: http://git-master/r/36351
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc4b424f1a55ffb71245f3a8330559258124e2a19

7 files changed, 20 insertions, 20 deletions

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index ac9e5a9eaa63..a53958789f48 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -33,13 +33,13 @@ obj-$(CONFIG_TEGRA_ARB_SEMAPHORE)       += arb_sema.o
 obj-y                                   += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra3_clocks.o
-ifneq ($(CONFIG_TEGRA_FPGA_PLATFORM),y)
+ifeq ($(CONFIG_TEGRA_SILICON_PLATFORM),y)
 obj-y                                   += dvfs.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_dvfs.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra3_dvfs.o
 endif
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_fuse.o
-ifneq ($(CONFIG_TEGRA_FPGA_PLATFORM),y)
+ifeq ($(CONFIG_TEGRA_SILICON_PLATFORM),y)
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra3_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra3_actmon.o
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 6d62efd1dd49..3513b6912131 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -118,7 +118,7 @@ void tegra_assert_system_reset(char mode, const char *cmd)
 static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
 	/* name		parent		rate		enabled */
 	{ "clk_m",	NULL,		0,		true },
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 	{ "pll_p",	NULL,		216000000,	true },
 	{ "pll_p_out1",	"pll_p",	28800000,	true },
@@ -180,10 +180,7 @@ void tegra_init_cache(void)
 	writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
 
 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
-	writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
-	writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
-#else
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
 	/* PL310 RAM latency is CPU dependent. NOTE: Changes here
 	   must also be reflected in __cortex_a9_l2x0_restart */
 
@@ -194,6 +191,9 @@ void tegra_init_cache(void)
 		writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
 		writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
 	}
+#else
+	writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
+	writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
 #endif
 
 	/* Enable PL310 double line fill feature. */
diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h
index 44d09225667f..2257871045bc 100644
--- a/arch/arm/mach-tegra/dvfs.h
+++ b/arch/arm/mach-tegra/dvfs.h
@@ -87,7 +87,7 @@ struct dvfs {
 	struct list_head reg_node;
 };
 
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
 void tegra_soc_init_dvfs(void);
 int tegra_enable_dvfs_on_clk(struct clk *c, struct dvfs *d);
 int dvfs_debugfs_init(struct dentry *clk_debugfs_root);
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index 65c43c6843a0..8ccb085870a4 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -32,7 +32,7 @@ enum tegra_chipid tegra_get_chipid(void);
 enum tegra_revision tegra_get_revision(void);
 const char *tegra_get_revision_name(void);
 
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
 
 int tegra_cpu_process_id(void);
 int tegra_core_process_id(void);
@@ -40,7 +40,7 @@ int tegra_cpu_speedo_id(void);
 int tegra_soc_speedo_id(void);
 void tegra_init_speedo_data(void);
 
-#else /* CONFIG_TEGRA_FPGA_PLATFORM */
+#else
 
 static inline int tegra_cpu_process_id(void) { return 0; }
 static inline int tegra_core_process_id(void) { return 0; }
@@ -48,4 +48,4 @@ static inline int tegra_cpu_speedo_id(void) { return 0; }
 static inline int tegra_soc_speedo_id(void) { return 0; }
 static inline void tegra_init_speedo_data(void) { }
 
-#endif /* CONFIG_TEGRA_FPGA_PLATFORM */
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index 2cc8b84d845e..f6d178cca412 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -38,7 +38,7 @@ enum tegra_clk_ex_param {
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
 int tegra_dvfs_set_rate(struct clk *c, unsigned long rate);
 #else
 static inline int tegra_dvfs_set_rate(struct clk *c, unsigned long rate)
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c
index 9602d404a6cc..5353fefa0c08 100644
--- a/arch/arm/mach-tegra/tegra3_clocks.c
+++ b/arch/arm/mach-tegra/tegra3_clocks.c
@@ -1674,7 +1674,7 @@ static int tegra3_plle_configure(struct clk *c, bool force_training)
 #if USE_PLLE_SS
 	/* configure spread spectrum coefficients */
 	/* FIXME: coefficients for 216MHZ input? */
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
 	if (input_rate == 12000000)
 #endif
 	{
@@ -2935,7 +2935,7 @@ static struct clk tegra_pll_p = {
 		.vco_max   = 1400000000,
 		.freq_table = tegra_pll_p_freq_table,
 		.lock_delay = 300,
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
 		.fixed_rate = 408000000,
 #else
 		.fixed_rate = 216000000,
@@ -3197,7 +3197,7 @@ static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
 	/* PLLE special case: use cpcon field to store cml divider value */
 	{ 12000000,  100000000, 150, 1,  18, 11},
 	{ 216000000, 100000000, 200, 18, 24, 13},
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
+#ifndef CONFIG_TEGRA_SILICON_PLATFORM
 	{ 13000000,  100000000, 200, 1,  26, 13},
 #endif
 	{ 0, 0, 0, 0, 0, 0 },
@@ -3542,7 +3542,7 @@ static struct clk tegra_clk_sbus_cmplx = {
 		.hclk = &tegra_clk_hclk,
 		.sclk_low = &tegra_pll_p_out4,
 		.sclk_high = &tegra_pll_m_out1,
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
 		.threshold = 204000000, /* exact factor of low range pll_p */
 #else
 		.threshold = 108000000, /* exact factor of low range pll_p */
diff --git a/arch/arm/mach-tegra/timer-t3.c b/arch/arm/mach-tegra/timer-t3.c
index f126af0a7653..4e03d02c7ef5 100644
--- a/arch/arm/mach-tegra/timer-t3.c
+++ b/arch/arm/mach-tegra/timer-t3.c
@@ -245,16 +245,16 @@ void __init tegra3_init_timer(u32 *offset, int *irq)
 #ifdef CONFIG_PM_SLEEP
 	/* For T30.A01 use INT_TMR_SHARED instead of INT_TMR6. */
 	if (((id & 0xFF00) >> 8) == 0x30) {
-#ifdef CONFIG_TEGRA_FPGA_PLATFORM
+#ifdef CONFIG_TEGRA_SILICON_PLATFORM
+		if (((id >> 16) & 0xf) == 1)
+			tegra_lp2wake_irq[3].irq = INT_TMR_SHARED;
+#else
 		void __iomem *emu_rev = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x860;
 		unsigned long reg = readl(emu_rev);
 		unsigned long netlist = reg & 0xFFFF;
 		unsigned long patch = (reg >> 16) & 0xFF;
 		if ((netlist == 12) && (patch < 14))
 			tegra_lp2wake_irq[3].irq = INT_TMR_SHARED;
-#else
-		if (((id >> 16) & 0xf) == 1)
-			tegra_lp2wake_irq[3].irq = INT_TMR_SHARED;
 #endif
 	}