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authorThierry Reding <treding@nvidia.com>2015-01-22 08:48:25 +0100
committerThierry Reding <treding@nvidia.com>2015-04-02 18:46:13 +0200
commitd29827484b9cf6026506a0e376fb5d246580ffd8 (patch)
tree04f12510e76ccb3a0270903d9c0721988c0ada1d
parent13a7a6ac0a11197edcd0f756a035f472b42cdf8b (diff)
drm/tegra: dc: Check for valid parent clock
Check that the desired parent clock is indeed a valid parent for the display controller clock. This is purely cosmetic at this point since the parent clocks are specified in DT and all the currently defined parents are in fact valid parents of the display controller clock. Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/gpu/drm/tegra/dc.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 1a52522f5da7..8746a9ce6a8f 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1177,6 +1177,9 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc,
{
struct tegra_dc_state *state = to_dc_state(crtc_state);
+ if (!clk_has_parent(dc->clk, clk))
+ return -EINVAL;
+
state->clk = clk;
state->pclk = pclk;
state->div = div;