diff options
| author | Raj Mailapalli <rmailapalli@nvidia.com> | 2010-04-13 10:11:33 +0530 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-04-20 15:44:52 -0700 |
| commit | 07d27e31879b316a52a562913c7fba0cca8a0db4 (patch) | |
| tree | 1ac68a0fb92cc25ebe9d45e6cf23ba0f34edc35a | |
| parent | 7085b74b8974dac8ac2c2e958f0098970d9b43ec (diff) | |
[ARM] tegra: fix errors in tegra pinmux tables for SPI, NAND, OWR
Bug 671189, 663161
Tested on Nand + android.
Change-Id: I518d8a1b57a9766dc69a115b1189789f054c2d0e
Reviewed-on: http://git-master/r/1088
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
| -rwxr-xr-x | arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c index 66459fcdc4c5..05921fd360b3 100755 --- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c +++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c @@ -41,8 +41,6 @@ #include "nvrm_clocks.h" #include "nvodm_query_pinmux.h" -// FIXME: None of the modules have reset configurations, yet. This should -// be fixed. static const NvU32 g_Ap20Mux_Uart1[] = { UNCONFIG(C,IRRX,UARTA,UARTB),UNCONFIG(C,IRTX,UARTA,UARTB), UNCONFIG(A,UAA,UARTA,MIPI_HS),UNCONFIG(A,UAB,UARTA,MIPI_HS), @@ -156,7 +154,7 @@ static const NvU32 g_Ap20Mux_Spi3[] = { * -spia of SPI2_MOSI as spi3_dout on mux: 2 under config 7. */ CONFIG(B,D,SPIA,SPI3),CONFIG(B,D,SPIF,SPI3), - CONFIG(B,D,SPIG,SPI3),CONFIG(B,D,SPIG,SPI3), CONFIGEND(), + CONFIG(B,D,SPIG,SPI3),CONFIG(B,D,SPIH,SPI3), CONFIGEND(), MODULEDONE(), }; @@ -393,7 +391,7 @@ static const NvU32 g_Ap20Mux_Nand[] = { CONFIGEND(), // config 1 CONFIG(A,A,ATA,NAND),CONFIG(A,A,ATB,NAND),CONFIG(A,A,ATC,NAND), - CONFIG(A,A,ATD,NAND),CONFIG(B,A,ATE,NAND),CONFIG(B,C,GMB,IDE), CONFIGEND(), + CONFIG(A,A,ATD,NAND),CONFIG(B,A,ATE,NAND),CONFIGEND(), //.config 2 CONFIG(A,A,ATA,NAND),CONFIG(A,A,ATB,NAND),CONFIG(A,A,ATC,NAND),CONFIGEND(), // config 3 @@ -744,7 +742,7 @@ static const NvU32 *g_Ap20MuxEtm[] = { }; static const NvU32 g_Ap20Mux_Owr[] = { - UNCONFIG(B,OWC,OWR,RSVD1),UNCONFIG(A,UAC,OWR,RSVD2),UNCONFIG(D,GPU,PWM,RSVD4), + // no reset here,it causes issue for pwm if we use otherthan gpu padgroup CONFIGEND(), // config 1 CONFIG(A,B,OWC,OWR),CONFIG(B,A,UAC,OWR),CONFIGEND(), |