diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-07-14 21:35:48 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-07-20 16:45:15 -0700 |
| commit | 25be81288a8513e5af18fa50a21921034b30a70f (patch) | |
| tree | c49b78c22f3cea9659931d075d58d436ae65e017 | |
| parent | 30115e75f5398a755f0d2755a5a38e1d6894656d (diff) | |
ARM: tegra: clock: Set Tegra3 LPDDR2 minimum rate to 25MHz
Change-Id: I8cd5cfef8a040ffa5f0959b5a294b25a21fcfa8b
Reviewed-on: http://git-master/r/41141
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.c | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index a238ef062743..c23a1211a2b8 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -3745,7 +3745,7 @@ static struct clk tegra_clk_emc = { .ops = &tegra_emc_clk_ops, .reg = 0x19c, .max_rate = 800000000, - .min_rate = 50000000, + .min_rate = 25000000, .inputs = mux_pllm_pllc_pllp_clkm, .flags = MUX | DIV_U71 | PERIPH_EMC_ENB, .u.periph = { diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c index 44a7009ad1da..3a7e64e7380b 100644 --- a/arch/arm/mach-tegra/tegra3_emc.c +++ b/arch/arm/mach-tegra/tegra3_emc.c @@ -43,6 +43,7 @@ static bool emc_enable; #endif module_param(emc_enable, bool, 0644); +#define EMC_MIN_RATE_DDR3 50000000 #define EMC_STATUS_UPDATE_TIMEOUT 100 #define TEGRA_EMC_TABLE_MAX_SIZE 16 @@ -847,6 +848,9 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) pr_err("Not supported DRAM type %u\n", dram_type); return; } + if (dram_type == DRAM_TYPE_DDR3) + emc->min_rate = EMC_MIN_RATE_DDR3; + reg = emc_readl(EMC_CFG_2) & (~EMC_CFG_2_MODE_MASK); reg |= ((dram_type == DRAM_TYPE_LPDDR2) ? EMC_CFG_2_PD_MODE : EMC_CFG_2_SREF_MODE) << EMC_CFG_2_MODE_SHIFT; |