diff options
| author | Bo Yan <byan@nvidia.com> | 2012-11-30 16:11:15 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:44:23 -0700 |
| commit | 39e4c2fc78467a5d6ecc4bf94bccb2987c13f9d1 (patch) | |
| tree | 31df1131b2690d080272705ab0bb9ced6277faa1 | |
| parent | c9208bc5c2dd2e7d874916f0cdfa4ce73e48e7c8 (diff) | |
ARM: mm: Enable NCSE feature for A15 only
Change-Id: If966ee69f1d5e4314f79685238ecff3c44eadac0
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/167879
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index f6c1348106f5..e3d2a3f61fc9 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -427,24 +427,24 @@ __v7_ca5mp_setup: __v7_ca9mp_setup: mov r10, #(1 << 0) @ TLB ops broadcasting b 1f -__v7_ca7mp_setup: __v7_ca15mp_setup: +#ifdef CONFIG_ARCH_TEGRA + mrc p15, 0, r0, c1, c0, 1 + orr r0, #(1<<24) @ Enable NCSE in ACTLR + mcr p15, 0, r0, c1, c0, 1 +#endif +__v7_ca7mp_setup: mov r10, #0 1: -#ifdef CONFIG_SMP || CONFIG_ARCH_TEGRA +#ifdef CONFIG_SMP ALT_SMP(mrc p15, 0, r0, c1, c0, 1) ALT_UP(mov r0, #(1 << 6)) @ fake it for UP tst r0, #(1 << 6) @ SMP/nAMP mode enabled? orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode orreq r0, r0, r10 @ Enable CPU-specific SMP bits -#ifdef CONFIG_ARCH_TEGRA - orr r0, #(1<<24) @ Enable non-cacheable streaming enhancement - mcr p15, 0, r0, c1, c0, 1 -#else mcreq p15, 0, r0, c1, c0, 1 #endif b __v7_setup -#endif __v7_pj4b_setup: #ifdef CONFIG_CPU_PJ4B |