diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2017-07-24 14:51:21 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 903824b3286317c91172693bf2af3a119088fb03 (patch) | |
| tree | f0c10b354fd0b66e18e0c1c8d451e0b2a5f29500 | |
| parent | 651018d16d67a89410d4c31c5c496772809765a0 (diff) | |
MLK-16077-2: clk: imx: update cm40 clock for imx8qxp
Add cm40 I2C clock for imx8qxp
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
| -rw-r--r-- | drivers/clk/imx/clk-imx8qxp.c | 6 | ||||
| -rw-r--r-- | include/dt-bindings/clock/imx8qxp-clock.h | 8 | ||||
| -rw-r--r-- | include/dt-bindings/soc/imx8_pd.h | 4 | ||||
| -rw-r--r-- | include/soc/imx8/imx8qxp/lpcg.h | 3 |
4 files changed, 20 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index b9d05506aa1e..77d3aeeb8f0d 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -142,6 +142,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) clks[IMX8QXP_IMG_PXL_CLK] = imx_clk_fixed("pxl_img_clk_root", SC_600MHZ); clks[IMX8QXP_HSIO_AXI_CLK] = imx_clk_fixed("axi_hsio_clk_root", SC_400MHZ); clks[IMX8QXP_HSIO_PER_CLK] = imx_clk_fixed("per_hsio_clk_root", SC_133MHZ); + clks[IMX8QXP_CM40_IPG_CLK] = imx_clk_fixed("ipg_cm40_clk_root", SC_132MHZ); clks[IMX8QXP_UART0_DIV] = imx_clk_divider_scu("uart0_div", SC_R_UART_0, SC_PM_CLK_PER); clks[IMX8QXP_UART0_IPG_CLK] = imx_clk_gate2_scu("uart0_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPUART_0_LPCG), 16, FUNCTION_NAME(PD_DMA_UART0)); @@ -512,6 +513,11 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) clks[IMX8QXP_HSIO_GPIO_CLK] = imx_clk_gate2_scu("hsio_gpio_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_GPIO_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_B)); clks[IMX8QXP_HSIO_PHY_X1_PCLK] = imx_clk_gate2_scu("hsio_phy_x1_pclk", "dummy", (void __iomem *)(HSIO_PHY_X1_LPCG), 0, FUNCTION_NAME(PD_HSIO_PCIE_B)); + /* CM40 */ + clks[IMX8QXP_CM40_I2C_DIV] = imx_clk_divider_scu("cm40_i2c_div", SC_R_M4_0_I2C, SC_PM_CLK_PER); + clks[IMX8QXP_CM40_I2C_CLK] = imx_clk_gate_scu("cm40_i2c_clk", "cm40_i2c_div", SC_R_M4_0_I2C, SC_PM_CLK_PER, (void __iomem *)(CM40_I2C_LPCG), 0, 0); + clks[IMX8QXP_CM40_I2C_IPG_CLK] = imx_clk_gate2_scu("cm40_i2c_ipg_clk", "ipg_cm40_clk_root", (void __iomem *)(CM40_I2C_LPCG), 16, FUNCTION_NAME(PD_CM40_I2C)); + /* Audio */ clks[IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV] = imx_clk_divider2_scu("aud_acm_aud_pll_clk0_div", "audio_pll0_clk", SC_R_AUDIO_PLL_0, SC_PM_CLK_MISC0); clks[IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV] = imx_clk_divider2_scu("aud_acm_aud_pll_clk1_div", "audio_pll1_clk", SC_R_AUDIO_PLL_1, SC_PM_CLK_MISC0); diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h index 96205ba0c158..a31c120dc0ae 100644 --- a/include/dt-bindings/clock/imx8qxp-clock.h +++ b/include/dt-bindings/clock/imx8qxp-clock.h @@ -523,5 +523,11 @@ #define IMX8QXP_MIPI1_LVDS_PHY_CLK 475 #define IMX8QXP_MIPI1_LIS_IPG_CLK 476 -#define IMX8QXP_CLK_END 477 +/* CM40 */ +#define IMX8QXP_CM40_IPG_CLK 477 +#define IMX8QXP_CM40_I2C_DIV 478 +#define IMX8QXP_CM40_I2C_CLK 479 +#define IMX8QXP_CM40_I2C_IPG_CLK 480 + +#define IMX8QXP_CLK_END 481 #endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */ diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h index 6e241e09e090..1483ac35f376 100644 --- a/include/dt-bindings/soc/imx8_pd.h +++ b/include/dt-bindings/soc/imx8_pd.h @@ -187,5 +187,9 @@ #define PD_HDMI_RX_I2C hdmi_rx_i2c #define PD_HDMI_RX_PWM hdmi_rx_pwm +#define PD_CM40 cm40_power_domain +#define PD_CM40_I2C cm40_i2c +#define PD_CM40_INTMUX cm40_intmux + #endif /* __DT_BINDINGS_IMX8_PD_H */ diff --git a/include/soc/imx8/imx8qxp/lpcg.h b/include/soc/imx8/imx8qxp/lpcg.h index 6cad103b0975..061454f5f225 100644 --- a/include/soc/imx8/imx8qxp/lpcg.h +++ b/include/soc/imx8/imx8qxp/lpcg.h @@ -177,5 +177,8 @@ #define NAND_LPCG 0x5B290000 #define EDMA_LPCG 0x5B2A0000 +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + #endif |