diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2017-07-03 13:02:57 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 9f82951dcd9f29704c1671d9e50013b0aaf44197 (patch) | |
| tree | 3c59fa10abf2d868614d46cdef62ce3d73213a9f | |
| parent | cef81d7bd7e0ba2bef3f1c7d0aa66a137df9643a (diff) | |
MLK-15343-1 ARM: imx: enable pcieb on imx8qm
Based on base board, enable pcieb lane1, enlarge
the CFG mapping space.
HSIO configuration is 1 lane PCIEA, 1 lane PCIEB and SATA.
PHY configurations:
PHY_X2_0 <------> PCIEA 1 lane
PHY_X2_1 <------> PCIEB 1 lane
PHY_X1 <------> SATA
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | 16 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | 42 |
2 files changed, 57 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts index 9a6d55cc113d..fd9b6a211301 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -423,6 +423,14 @@ SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x00000021 >; }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x00000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x00000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x00000021 + >; + }; }; }; @@ -812,3 +820,11 @@ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi index 734d587bf0a7..877b05fe16e1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -2438,7 +2438,7 @@ pciea: pcie@0x5f000000 { compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; reg = <0x0 0x5f000000 0x0 0x10000>, /* Controller reg */ - <0x0 0x6ff00000 0x0 0x10000>; /* PCI cfg space */ + <0x0 0x6ff00000 0x0 0x80000>; /* PCI cfg space */ reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; @@ -2475,6 +2475,46 @@ status = "disabled"; }; + pcieb: pcie@0x5f010000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg */ + <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + power-domains = <&pd_pcie1>; + fsl,max-link-speed = <3>; + hsio-cfg = <PCIEAX1PCIEBX1SATA>; + hsio = <&hsio>; + ctrl-id = <1>; /* pciea */ + cpu-base-addr = <0x80000000>; + status = "disabled"; + }; + imx_ion { compatible = "fsl,mxc-ion"; fsl,heap-id = <0>; |