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| author | Max Krummenacher <max.krummenacher@toradex.com> | 2024-02-20 11:20:08 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2024-02-20 11:20:08 +0100 |
| commit | aaf9dc6089bc3ce6a648ad9a38b96f07f2aff314 (patch) | |
| tree | 5143293e4da9ed87287279a41cfd8d5d900a32c0 | |
| parent | 35ecaa3632bff102decb9f2277cf99150b2bf690 (diff) | |
Revert "PCI: layerscape: Add workaround for lost link capabilities during reset"
This reverts commit cefcb002c5c9bc107daee807e25636a9afc7aba7.
Downstream NXP and stable have deviated to far, do not pull this in.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | drivers/pci/controller/dwc/pci-layerscape-ep.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index dd7d74fecc48..5b27554e071a 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -45,7 +45,6 @@ struct ls_pcie_ep { struct pci_epc_features *ls_epc; const struct ls_pcie_ep_drvdata *drvdata; int irq; - u32 lnkcap; bool big_endian; }; @@ -74,7 +73,6 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) struct ls_pcie_ep *pcie = dev_id; struct dw_pcie *pci = pcie->pci; u32 val, cfg; - u8 offset; val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); @@ -83,19 +81,6 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) return IRQ_NONE; if (val & PEX_PF0_PME_MES_DR_LUD) { - - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - - /* - * The values of the Maximum Link Width and Supported Link - * Speed from the Link Capabilities Register will be lost - * during link down or hot reset. Restore initial value - * that configured by the Reset Configuration Word (RCW). - */ - dw_pcie_dbi_ro_wr_en(pci); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); - dw_pcie_dbi_ro_wr_dis(pci); - cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); cfg |= PEX_PF0_CFG_READY; ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); @@ -229,7 +214,6 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) struct ls_pcie_ep *pcie; struct pci_epc_features *ls_epc; struct resource *dbi_base; - u8 offset; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); @@ -266,9 +250,6 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - ret = dw_pcie_ep_init(&pci->ep); if (ret) return ret; |