diff options
| author | Bo Yan <byan@nvidia.com> | 2012-11-29 11:33:44 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:44:30 -0700 |
| commit | b68dff902ee29cd65c5272a101b66c6eb5fa0442 (patch) | |
| tree | ef65b34ab6ca3df570f4e64c45f383773f4bcf20 | |
| parent | 384c953dfed129c15363366bf54fb19ff2f26e5d (diff) | |
ARM: mm: restore counter enable register
Change-Id: I2433e53175e79d558d76a7c37b10de9175d7b1b0
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/167385
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index e3d2a3f61fc9..030278ab068b 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -130,7 +130,7 @@ ENDPROC(cpu_v7_dcache_clean_area) #endif .globl cpu_v7_suspend_size -.equ cpu_v7_suspend_size, (4 * 15) + cpu_v7_debug_suspend_size +.equ cpu_v7_suspend_size, (4 * 17) + cpu_v7_debug_suspend_size #ifdef CONFIG_ARM_CPU_SUSPEND ENTRY(cpu_v7_do_suspend) stmfd sp!, {r3 - r10, lr} @@ -145,7 +145,9 @@ ENTRY(cpu_v7_do_suspend) mrc p15, 0, r7, c9, c13, 2 @ PMXEVCNTR, event counter mrc p15, 0, r8, c9, c13, 1 @ PMXEVTYPER or PMCCFILTR mrc p15, 0, r9, c9, c13, 0 @ PMCCNTR, cycle counter - stmia r0!, {r4 - r9} + mrc p15, 0, r10, c9, c12, 0 @ PMCR, control register + mrc p15, 0, r11, c9, c12, 1 @ PMCNTENSET, counter enable set + stmia r0!, {r4 - r11} mrc p15, 0, r6, c3, c0, 0 @ Domain ID mrc p15, 0, r7, c2, c0, 1 @ TTB 1 @@ -256,13 +258,15 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r6, c15, c0, 1 @ diag #endif - ldmia r0!, {r4 - r9} + ldmia r0!, {r4 - r11} mcr p15, 0, r4, c9, c14, 2 @ PMINTENCLR mcr p15, 0, r5, c9, c14, 0 @ PMUSEREN mcr p15, 0, r6, c9, c12, 5 @ PMSELR, event counter selection mcr p15, 0, r7, c9, c13, 2 @ PMXEVCNTR, event counter mcr p15, 0, r8, c9, c13, 1 @ PMXEVTYPER or PMCCFILTR mcr p15, 0, r9, c9, c13, 0 @ PMCCNTR, cycle counter + mcr p15, 0, r10, c9, c12, 0 @ PMCR, control register + mcr p15, 0, r11, c9, c12, 1 @ PMCNTENSET, counter enable set ldmia r0!, {r6 - r11} mcr p15, 0, r6, c3, c0, 0 @ Domain ID |