diff options
| author | Richard Zhu <r65037@freescale.com> | 2014-07-09 17:11:34 +0800 |
|---|---|---|
| committer | Richard Zhu <r65037@freescale.com> | 2014-07-09 17:21:56 +0800 |
| commit | bf43cf9c6c56da8862a2b2cdd461f78cd80632b8 (patch) | |
| tree | 06e440d1ea4784b65cba5bc0b45ea3eee7ecab81 | |
| parent | 6e5694927530b4ea5de0c79860f6231351413234 (diff) | |
ENGR00320021-3 pcie:add the pcie reg dump
add the pcie related gpr/anatop reg dump
into pcie driver
Signed-off-by: Richard Zhu <r65037@freescale.com>
| -rw-r--r-- | drivers/pci/host/pci-imx6.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index bfc34993e257..ed991a22020b 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -104,6 +104,35 @@ static inline bool is_imx6sx_pcie(struct imx6_pcie *imx6_pcie) return imx6_pcie->data == &imx6sx_pcie_data; } +#ifdef DEBUG +static int pcie_reg_dump(struct imx6_pcie *imx6_pcie) +{ + u32 val; + struct regmap *anatop_g; + + /* GPRs registers */ + regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &val); + pr_info("<F> %s <L> %d gpr1 0x%08x.\n", __func__, __LINE__, val); + regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, &val); + pr_info("<F> %s <L> %d gpr5 0x%08x.\n", __func__, __LINE__, val); + regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, &val); + pr_info("<F> %s <L> %d gpr8 0x%08x.\n", __func__, __LINE__, val); + regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &val); + pr_info("<F> %s <L> %d gpr12 0x%08x.\n", __func__, __LINE__, val); + regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR13, &val); + pr_info("<F> %s <L> %d gpr13 0x%08x.\n", __func__, __LINE__, val); + + /* anatop registers: pll6_enet, misc1 */ + anatop_g = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); + if (IS_ERR(anatop_g)) + pr_err("failed to find fsl,imx6sx-anatop regmap\n"); + regmap_read(anatop_g, 0xe0, &val); + pr_info("<F> %s <L> %d pll6_enet 0x%08x.\n", __func__, __LINE__, val); + regmap_read(anatop_g, 0x160, &val); + pr_info("<F> %s <L> %d misc1 0x%08x.\n", __func__, __LINE__, val); +} +#endif + static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) { u32 val; @@ -408,6 +437,9 @@ static void imx6_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); +#ifdef DEBUG + pcie_reg_dump(imx6_pcie); +#endif regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); |