diff options
| author | Alison Wang <b18965@freescale.com> | 2013-08-15 16:01:51 +0800 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2014-10-01 18:58:28 +0200 |
| commit | f4c3c5a2292b62b3f50e4d73b369e946de6535cc (patch) | |
| tree | ab54aca13533e1bce11c9538e053c8cf7a973568 | |
| parent | 44bdd7bf9b192fe56a04d4428081a4e264a4e44c (diff) | |
ARM: dts: vf610-twr: Enable DCU and TCON devices
This patch enables DCU and TCON devices for Vybrid VF610 TOWER board.
Signed-off-by: Alison Wang <b18965@freescale.com>
[moved pinmux to Tower configuration]
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | arch/arm/boot/dts/vf610-twr.dts | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index 189b6975fe7d..f84e81821967 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -119,6 +119,34 @@ status = "okay"; }; +&dcu0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dcu0_1>; + display = <&display>; + status = "okay"; + + display: display@0 { + bits-per-pixel = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: nl4827hc19 { + clock-frequency = <10870000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hfront-porch = <2>; + vback-porch = <1>; + vfront-porch = <1>; + hsync-len = <41>; + vsync-len = <2>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + &fec0 { phy-mode = "rmii"; pinctrl-names = "default"; @@ -157,6 +185,39 @@ >; }; + pinctrl_dcu0_1: dcu0grp_1 { + fsl,pins = < + VF610_PAD_PTE0__DCU0_HSYNC 0x42 + VF610_PAD_PTE1__DCU0_VSYNC 0x42 + VF610_PAD_PTE2__DCU0_PCLK 0x42 + VF610_PAD_PTE4__DCU0_DE 0x42 + VF610_PAD_PTE5__DCU0_R0 0x42 + VF610_PAD_PTE6__DCU0_R1 0x42 + VF610_PAD_PTE7__DCU0_R2 0x42 + VF610_PAD_PTE8__DCU0_R3 0x42 + VF610_PAD_PTE9__DCU0_R4 0x42 + VF610_PAD_PTE10__DCU0_R5 0x42 + VF610_PAD_PTE11__DCU0_R6 0x42 + VF610_PAD_PTE12__DCU0_R7 0x42 + VF610_PAD_PTE13__DCU0_G0 0x42 + VF610_PAD_PTE14__DCU0_G1 0x42 + VF610_PAD_PTE15__DCU0_G2 0x42 + VF610_PAD_PTE16__DCU0_G3 0x42 + VF610_PAD_PTE17__DCU0_G4 0x42 + VF610_PAD_PTE18__DCU0_G5 0x42 + VF610_PAD_PTE19__DCU0_G6 0x42 + VF610_PAD_PTE20__DCU0_G7 0x42 + VF610_PAD_PTE21__DCU0_B0 0x42 + VF610_PAD_PTE22__DCU0_B1 0x42 + VF610_PAD_PTE23__DCU0_B2 0x42 + VF610_PAD_PTE24__DCU0_B3 0x42 + VF610_PAD_PTE25__DCU0_B4 0x42 + VF610_PAD_PTE26__DCU0_B5 0x42 + VF610_PAD_PTE27__DCU0_B6 0x42 + VF610_PAD_PTE28__DCU0_B7 0x42 + >; + }; + pinctrl_dspi0: dspi0grp { fsl,pins = < VF610_PAD_PTB19__DSPI0_CS0 0x1182 @@ -264,6 +325,10 @@ status = "okay"; }; +&tcon0 { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; |