tegra RM: Separated EMC scaling floors per SDRAM type.

Separated EMC frequency low corners for LPDDR2 and DDR2. For now, kept
both limits the same as common floor before (50MHz).

Change-Id: Ieaa238f78ceb5a7f4f238ffe78c576bb7d5840b1
Reviewed-on: http://git-master/r/906
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

3 files changed, 41 insertions, 1 deletions

diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
index b525e1b16bae..ae73a896a722 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
@@ -60,6 +60,30 @@
 // EMC MODULE INTERFACES
 /*****************************************************************************/
 
+void NvRmPrivAp20EmcMinFreqSet(NvRmDfs* pDfs)
+{
+    NvRmFreqKHz f;
+    NvU32 RegValue = NV_REGR(pDfs->hRm,
+        NvRmPrivModuleID_ExternalMemoryController, 0, EMC_FBIO_CFG5_0);
+
+    switch (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_TYPE, RegValue))
+    {
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2:
+            f = NVRM_AP20_LPDDR2_MIN_KHZ;
+            break;
+
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2:
+            f = NVRM_AP20_DDR2_MIN_KHZ;
+            break;
+
+        default:
+            f = 0;
+            NV_ASSERT(!"Not supported DRAM type");
+    }
+    pDfs->DfsParameters[NvRmDfsClockId_Emc].MinKHz =
+        NV_MAX(pDfs->DfsParameters[NvRmDfsClockId_Emc].MinKHz, f);
+}
+
 NvError NvRmPrivAp20EmcMonitorsInit(NvRmDfs* pDfs)
 {
     NvU32 RegValue;
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
index 13ead9968fed..dcd1be33422b 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
@@ -190,7 +190,7 @@ extern "C"
  */
 #define NVRM_DFS_PARAM_EMC_AP20 \
     NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
-    50000,  /* Minimum domain frequency 50 MHz */ \
+    18000,  /* Minimum domain frequency 18 MHz (for all SDRAM types) */ \
     1000,   /* Frequency change upper band 1 MHz */ \
     1000,   /* Frequency change lower band 1 MHz */ \
     {          /* RT starvation control parameters */ \
@@ -207,6 +207,9 @@ extern "C"
     0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
     1       /* NRT idle cycles threshold = 1 */ 
 
+// Defines minimum scaling limit for each supported SDRAM type
+#define NVRM_AP20_DDR2_MIN_KHZ (50000)
+#define NVRM_AP20_LPDDR2_MIN_KHZ (50000)
 
 /**
  * Defines CPU frequency threshold for slave CPU1 power management:
@@ -233,6 +236,14 @@ extern "C"
 /*****************************************************************************/
 
 /**
+ * Set minimum EMC frequency based on the SDRAM type selected by current EMC
+ * configuration.
+ *
+ * @param pDfs - A pointer to DFS structure.
+ */
+void NvRmPrivAp20EmcMinFreqSet(NvRmDfs* pDfs);
+
+/**
  * Initializes activity monitors within the DFS module. Only activity
  * monitors are affected. The rest of module's h/w is preserved.
  * 
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
index ce8601c06e23..9f73c1b2b6e6 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
@@ -766,6 +766,11 @@ static void DfsParametersInit(NvRmDfs* pDfs)
             break;
     }
 
+    // Adjust minimum frequency boundary for EMC as required for
+    // particular SDRAM type
+    if (pDfs->hRm->ChipId.Id == 0x20)
+        NvRmPrivAp20EmcMinFreqSet(pDfs);
+
     // CPU clock H/w limits
     pClimits = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu);
     HwLimitsKHz[NvRmDfsClockId_Cpu] = *pClimits;