diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2012-08-27 13:53:50 +0800 |
|---|---|---|
| committer | Xinyu Chen <xinyu.chen@freescale.com> | 2012-08-27 16:07:38 +0800 |
| commit | e19c2ff52fd37c37ac9bffedd6deda5de76caddb (patch) | |
| tree | 77a571fa252d879dd15c9fc33f7383af1290c67f | |
| parent | e61df589a843d28483c6d94a9d7c0b3517e6e832 (diff) | |
ENGR00221457 MX6DL clock:Set PLL3_PFD_540M to 540MHz
This patch sets PLL3_PFD_540M clock frequency to 540MHz
so that IPU and VPU clock can reach 270MHz.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 93b60ac679e3..86587b5eb2e2 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -5394,6 +5394,8 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* on mx6dl gpu2d_axi_clk source from mmdc0 directly */ clk_set_parent(&gpu2d_axi_clk, &mmdc_ch0_axi_clk[0]); + clk_set_rate(&pll3_pfd_540M, 540000000); + clk_set_parent(&ipu1_clk, &pll3_pfd_540M); /* pxp & epdc */ clk_set_parent(&ipu2_clk, &pll2_pfd_400M); |