diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2012-04-13 18:10:14 +0800 |
|---|---|---|
| committer | Liu Ying <Ying.Liu@freescale.com> | 2012-04-16 16:09:42 +0800 |
| commit | 438b53326d0eb63f51587118fb88fa5832cd7c8f (patch) | |
| tree | ccf2e7bf1d460bab223828d039d72baf1da656c6 | |
| parent | 5327f3f9288fc2682650b5afda44e2512ce865f3 (diff) | |
ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1
This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit c340ccfbc3d1ec6bc3d642ea2009c8e25247e4bc)
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index dd54d18234ad..889447b77076 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -5157,12 +5157,13 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* on mx6dl, max ipu clock is 274M */ clk_set_parent(&ipu1_clk, &pll3_pfd_540M); - clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M); - clk_set_parent(&ldb_di1_clk, &pll2_pfd_352M); } if (cpu_is_mx6q()) clk_set_parent(&gpu2d_core_clk[0], &pll3_usb_otg_main_clk); + clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M); + clk_set_parent(&ldb_di1_clk, &pll2_pfd_352M); + /* PCLK camera - J5 */ clk_set_parent(&clko2_clk, &osc_clk); clk_set_rate(&clko2_clk, 2400000); |