tegra l2 cache: minor code shuffling

Also use l2 cache code only if it is enabled via config. This is useful
when running with l2 cache disabled.
Tested on Harmony + Android for LP0 with l2 cache enabled.

Change-Id: I3c6c77e968497a34a92405080eb5d2b1834ed4ab
Reviewed-on: http://git-master/r/1283
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>

3 files changed, 26 insertions, 32 deletions

diff --git a/arch/arm/mach-tegra/idle-t2.c b/arch/arm/mach-tegra/idle-t2.c
index d9d66b6989db..0c37b0686f4e 100644
--- a/arch/arm/mach-tegra/idle-t2.c
+++ b/arch/arm/mach-tegra/idle-t2.c
@@ -43,7 +43,7 @@ extern NvU32 g_ArmPerif;
 extern NvU32 g_enterLP2PA;
 extern volatile void *g_pPMC, *g_pAHB, *g_pCLK_RST_CONTROLLER, *g_pRtc;
 extern volatile void *g_pEMC, *g_pMC, *g_pAPB_MISC, *g_pIRAM, *g_pTimerus;
-extern volatile void *g_pPL310;
+
 #ifdef CONFIG_WAKELOCK
 extern struct wake_lock main_wake_lock;
 #endif
@@ -214,18 +214,6 @@ void __init NvAp20InitFlowController(void)
         return;
     }
 
-    NvRmModuleGetBaseAddress(s_hRmGlobal,
-        NVRM_MODULE_ID(NvRmPrivModuleID_Pl310, 0), &pa, &len);
-
-    if (NvRmPhysicalMemMap(pa, len, NVOS_MEM_READ_WRITE,
-            NvOsMemAttribute_Uncached,
-            (void**)&g_pPL310)!=NvSuccess)
-    {
-        printk(KERN_INFO "failed to map pl310; DVFS will not function"
-               " correctly as a result\n");
-        return;
-    }
-
 #if NV_KBC_INTERRUPT_WORKAROUND
     NvRmModuleGetBaseAddress(s_hRmGlobal,
         NVRM_MODULE_ID(NvRmModuleID_Kbc, 0), &pa, &len);
diff --git a/arch/arm/mach-tegra/init_common.c b/arch/arm/mach-tegra/init_common.c
index 397e6c6df4ad..d04d113e85aa 100644
--- a/arch/arm/mach-tegra/init_common.c
+++ b/arch/arm/mach-tegra/init_common.c
@@ -858,13 +858,29 @@ fail:
 #else
 #include <asm/hardware/cache-l2x0.h>
 #include "ap20/arpl310.h"
+extern volatile void *g_pPL310;
 void tegra_pl310_init(void)
 {
     NvRmPhysAddr CachePa;
-    NvU32 Len;
-    volatile NvU8 *pCache = NULL;
+    NvU32 Len, AuxValue;
 
-    NvU32 AuxValue =
+    if (!g_pPL310)
+    {
+        if (!NvRmModuleGetNumInstances(s_hRmGlobal, NvRmPrivModuleID_Pl310))
+            return;
+
+        NvRmModuleGetBaseAddress(s_hRmGlobal,
+            NVRM_MODULE_ID(NvRmPrivModuleID_Pl310, 0), &CachePa, &Len);
+
+        if (NvRmPhysicalMemMap(CachePa, Len, NVOS_MEM_READ_WRITE,
+                NvOsMemAttribute_Uncached, (void **)&g_pPL310)!=NvSuccess)
+        {
+            printk(__FILE__ ":%d failed to map PL310\n", __LINE__);
+            return;
+        }
+    }
+
+    AuxValue =
         NV_DRF_NUM(PL310, AUXILIARY_CONTROL, FULL_LINE_OF_ZERO, 1) |
         NV_DRF_NUM(PL310, AUXILIARY_CONTROL, SO_DEV_HIGH_PRIORITY, 0) |
         /* FIXME:  Read performance tests show ~8-10% performance loss (uniprocessor
@@ -883,25 +899,13 @@ void tegra_pl310_init(void)
         NV_DRF_DEF(PL310, AUXILIARY_CONTROL, FORCE_WRITE_ALLOCATE, DISABLED) |
         NV_DRF_NUM(PL310, AUXILIARY_CONTROL, SHARED_ATTRIBUTE_OVERRIDE, 0) |
         NV_DRF_NUM(PL310, AUXILIARY_CONTROL, EARLY_BRESP, 1);
-  
-    if (!NvRmModuleGetNumInstances(s_hRmGlobal, NvRmPrivModuleID_Pl310))
-        return;
-
-    NvRmModuleGetBaseAddress(s_hRmGlobal,
-        NVRM_MODULE_ID(NvRmPrivModuleID_Pl310, 0), &CachePa, &Len);
 
-    if (NvRmPhysicalMemMap(CachePa, Len, NVOS_MEM_READ_WRITE,
-            NvOsMemAttribute_Uncached, (void **)&pCache)!=NvSuccess)
-    {
-        printk(__FILE__ ":%d failed to map PL310\n", __LINE__);
-        return;
-    }
-
-    NV_WRITE32(pCache + PL310_TAG_RAM_LATENCY_0,
+    NV_WRITE32(g_pPL310 + PL310_TAG_RAM_LATENCY_0,
         NV_DRF_DEF(PL310, TAG_RAM_LATENCY, SETUP, SW_DEFAULT) |
         NV_DRF_DEF(PL310, TAG_RAM_LATENCY, READ, SW_DEFAULT) |
         NV_DRF_DEF(PL310, TAG_RAM_LATENCY, WRITE, SW_DEFAULT));
-    NV_WRITE32(pCache + PL310_DATA_RAM_LATENCY_0,
+
+    NV_WRITE32(g_pPL310 + PL310_DATA_RAM_LATENCY_0,
         NV_DRF_DEF(PL310, DATA_RAM_LATENCY, SETUP, SW_DEFAULT) |
         NV_DRF_DEF(PL310, DATA_RAM_LATENCY, READ, SW_DEFAULT) |
         NV_DRF_DEF(PL310, DATA_RAM_LATENCY, WRITE, SW_DEFAULT));
@@ -926,7 +930,7 @@ void tegra_pl310_init(void)
         MCR(p15, 0, Reg, c1, c0, 1);
         local_irq_restore(flags);
     }
-    l2x0_init((void __iomem *)pCache, AuxValue, 0x8200c3fe);    
+    l2x0_init((void __iomem *)g_pPL310, AuxValue, 0x8200c3fe);
 }
 #endif
 
diff --git a/arch/arm/mach-tegra/power-lp.S b/arch/arm/mach-tegra/power-lp.S
index 49a701bbde4b..80453eecbc2d 100644
--- a/arch/arm/mach-tegra/power-lp.S
+++ b/arch/arm/mach-tegra/power-lp.S
@@ -151,6 +151,7 @@ ArmCortexA9Saved:
 	ldr	r3, [r3]	//R3 = g_pPMC
 	str	r1, [r3, #APBDEV_PMC_SCRATCH39_0]
 
+#if (defined(CONFIG_CACHE_PL310) || defined(CONFIG_CACHE_L2X0))
 	//Flush L2 rams for LP0
 	ldr	r1, =g_pPL310
 	ldr	r1, [r1]
@@ -205,6 +206,7 @@ unlock_all_ways:
 
 	cmp	r10, r2
 	bne	unlock_all_ways
+#endif
 
 copy_to_iram:
 	//Copy the low power core to IRAM using 8x4 block moves.