tegra: Avoid the use of literals in assembly code

Literals can be problematic in certain types of code.
Avoid them by taking advantage of ARMv7 architecture features.

Change-Id: I0784a94e82b1bfcdefe857e65a22de68f2acf976
Reviewed-on: http://git-master/r/1255
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

2 files changed, 60 insertions, 3 deletions

diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index dadad41a2008..1889f3f16d4c 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -21,6 +21,7 @@
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
+#include "nvmacro.h"
 
 	 .section ".text.head", "ax"
 	__CPUINIT
@@ -40,10 +41,10 @@ ENTRY(v7_invalidate_l1)
 	mcr	p15, 2, r0, c0, c0, 0
 	mrc	p15, 1, r0, c0, c0, 0
 
-	ldr	r1, =0x7fff
+	movw	r1, #0x7fff
 	and	r2, r1, r0, lsr #13
 
-	ldr	r1, =0x3ff
+	movw	r1, #0x3ff
 
 	and	r3, r1, r0, lsr #3	@ NumWays - 1
 	add	r2, r2, #1		@ NumSets
@@ -83,7 +84,7 @@ ENTRY(tegra_secondary_startup)
 	mrc	p15, 0, r0, c0, c0, 5	@ mpidr
 	and	r0, r0, #15
 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
-	ldr	r1, =0x6000f100
+	MOV32	r1, 0x6000f100
 #else
 #error "Invalid Tegra SoC family selection"
 #endif
diff --git a/arch/arm/mach-tegra/include/nvmacro.h b/arch/arm/mach-tegra/include/nvmacro.h
new file mode 100644
index 000000000000..e385c44fad35
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvmacro.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVMACRO_H
+#define INCLUDED_NVMACRO_H
+
+#if __ASSEMBLY__
+
+/**
+ * MOV32 macro to move a 32-bit value into a register without
+ * the use of literals.
+ *
+ *  	MOV32 reg, val
+ *
+ * Where "reg" is a register (R0-R14), and value is an absolute
+ * or relocatable value. Use of # is not required for absolute
+ * values and = should not be used for relocatable values.
+ */
+
+	.macro	MOV32	reg:req, val:req
+	movw	\reg, #:lower16:\val
+	movt	\reg, #:upper16:\val
+	.endm
+
+#endif	/* __ASSEMBLY__ */
+#endif	/* INCLUDED_tegra_macro_H */
+