diff options
| author | Nitin Garg <nitin.garg@freescale.com> | 2012-12-21 13:10:24 -0600 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2012-12-21 13:10:24 -0600 |
| commit | f47b3e32af5a1ea28d8900f788e0c4ac33208e98 (patch) | |
| tree | ea0f2b44fd7e33f3f7ea1511ed50b13420f1e4f7 | |
| parent | 09923d78ab3fc861fc4ff510ff9b5dcf4c348df6 (diff) | |
ENGR00238053: Fix the bug in Fuse read for VPU and GPU disablers of iMX53
Fix the bug in Fuse read for VPU and GPU disablers of iMX53. The
disablers are located at Fuase Bank 0. Also need to enable the clks
before reading the IIM.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx5/check_fuse.c | 42 | ||||
| -rwxr-xr-x | arch/arm/plat-mxc/include/mach/mx53.h | 1 |
2 files changed, 39 insertions, 4 deletions
diff --git a/arch/arm/mach-mx5/check_fuse.c b/arch/arm/mach-mx5/check_fuse.c index 2b607c095232..4dfc3e7bb814 100644 --- a/arch/arm/mach-mx5/check_fuse.c +++ b/arch/arm/mach-mx5/check_fuse.c @@ -19,6 +19,8 @@ #include <linux/io.h> #include <linux/module.h> +#include <linux/clk.h> +#include <linux/err.h> #include <mach/hardware.h> #include <mach/check_fuse.h> @@ -26,13 +28,29 @@ int mxc_fuse_get_gpu_status(void) { void __iomem *reg_base = NULL; u32 reg_val = 0; - int bit_status = 0; + int bit_status = 0, err; + struct clk *iim_clk; if (cpu_is_mx53() || cpu_is_mx51()) { + iim_clk = clk_get(NULL, "iim_clk"); + if (IS_ERR(iim_clk)) { + printk(KERN_ERR "GPU no IIM ref clock.\n"); + return 1; + } + err = clk_enable(iim_clk); + if (err) { + printk(KERN_ERR "GPU can't enable IIM ref clock.\n"); + clk_put(iim_clk); + return 1; + } + reg_base = MX53_IO_ADDRESS(MX53_IIM_BASE_ADDR); - reg_val = readl(reg_base + MXC_IIM_MX5_DISABLERS_OFFSET); + reg_val = readl(reg_base + MXC_IIM_MX53_BANK_AREA_0_OFFSET + + MXC_IIM_MX5_DISABLERS_OFFSET); bit_status = (reg_val & MXC_IIM_MX5_DISABLERS_GPU_MASK) >> MXC_IIM_MX5_DISABLERS_GPU_SHIFT; + clk_disable(iim_clk); + clk_put(iim_clk); } else if (cpu_is_mx50()) { reg_base = ioremap(MX50_OCOTP_CTRL_BASE_ADDR, SZ_8K); reg_val = readl(reg_base + FSL_OCOTP_MX5_CFG2_OFFSET); @@ -48,13 +66,29 @@ int mxc_fuse_get_vpu_status(void) { void __iomem *reg_base = NULL; u32 reg_val = 0; - int bit_status = 0; + int bit_status = 0, err; + struct clk *iim_clk; if (cpu_is_mx53()) { + iim_clk = clk_get(NULL, "iim_clk"); + if (IS_ERR(iim_clk)) { + printk(KERN_ERR "VPU no IIM ref clock.\n"); + return 1; + } + err = clk_enable(iim_clk); + if (err) { + printk(KERN_ERR "VPU can't enable IIM ref clock.\n"); + clk_put(iim_clk); + return 1; + } + reg_base = MX53_IO_ADDRESS(MX53_IIM_BASE_ADDR); - reg_val = readl(reg_base + MXC_IIM_MX5_DISABLERS_OFFSET); + reg_val = readl(reg_base + MXC_IIM_MX53_BANK_AREA_0_OFFSET + + MXC_IIM_MX5_DISABLERS_OFFSET); bit_status = (reg_val & MXC_IIM_MX5_DISABLERS_VPU_MASK) >> MXC_IIM_MX5_DISABLERS_VPU_SHIFT; + clk_disable(iim_clk); + clk_put(iim_clk); } return (1 == bit_status); diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 13c6f3bb7167..ca53d8b05615 100755 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -410,6 +410,7 @@ #define MXC_IIM_MX51_BANK_END_ADDR 0x147c #define MXC_IIM_MX53_BANK_START_ADDR 0x0800 #define MXC_IIM_MX53_BANK_END_ADDR 0x183c +#define MXC_IIM_MX53_BANK_AREA_0_OFFSET 0x800 #define MXC_IIM_MX53_BANK_AREA_1_OFFSET 0xc00 #define MXC_IIM_MX53_MAC_ADDR_OFFSET 0x24 |