dtb: move trdx pinmux definitions into trdx filesColibri_iMX6_LinuxImageV2.3Beta4_20141113Apalis_iMX6_LinuxImageV2.3Beta3_20141031

The Freescale provided files imx6qdl.dtsi, imx6q.dtsi provide among
other things pinmux definitions.
We added missing definitions to these files, however that could
become a merging nightmare in the future.
Move our additions into apalis/colibri files and use names which
likely do not collide with future upstream additions.

6 files changed, 388 insertions, 294 deletions

diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 59dd4f281c14..8735e99ef611 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -23,7 +23,7 @@
 
 	aliases {
 		rtc0 = &rtc_i2c;
-		rtc1 = &snvs_rtc;
+		rtc1 = "/soc/aips-bus@02000000/snvs@020cc000/snvs-rtc-lp@34";
 	};
 
 	aliases {
diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
index 446c08f0324f..9026d54f4fcc 100644
--- a/arch/arm/boot/dts/imx6q-apalis-eval.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
@@ -23,7 +23,7 @@
 
 	aliases {
 		rtc0 = &rtc_i2c;
-		rtc1 = &snvs_rtc;
+		rtc1 = "/soc/aips-bus@02000000/snvs@020cc000/snvs-rtc-lp@34";
 	};
 
 	aliases {
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index af7e6cdf60bb..580631278e79 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -240,29 +240,5 @@
 				MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23  0x10
 			>;
 		};
-		pinctrl_ipu2_2: ipu2grp-2 {
-			fsl,pins = <
-				MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xD1
-				MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xD1
-				MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xD1
-				MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xD1
-				MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xF9
-				MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xF9
-				MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xF9
-				MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xF9
-				MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xF9
-				MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xF9
-				MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xF9
-				MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xF9
-				MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xF9
-				MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xF9
-				MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xF9
-				MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xF9
-				MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xF9
-				MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xF9
-				MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xF9
-				MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xF9
-			>;
-		};
 	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index bcf5aaca94bb..ca75b8e4e1d7 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -59,7 +59,7 @@
 		disp_id = <1>;
 		default_ifmt = "RGB24";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ipu1_5>;
+		pinctrl-0 = <&pinctrl_ipu1_t1>;
 		status = "disabled";
 	};
 
@@ -242,7 +242,7 @@
 		disp_id = <0>;
 		default_ifmt = "RGB565";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ipu2_2>;
+		pinctrl-0 = <&pinctrl_ipu2_t1>;
 		status = "disabled";
 	};
 
@@ -254,7 +254,7 @@
 
 &audmux {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_audmux_4 &pinctrl_audmux_mclk_1>;
+	pinctrl-0 = <&pinctrl_audmux_t1 &pinctrl_audmux_mclk_1>;
 	status = "okay";
 };
 
@@ -263,7 +263,7 @@
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio5 25 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1_3 &pinctrl_spi_cs1>;
+	pinctrl-0 = <&pinctrl_ecspi1_t1 &pinctrl_spi_cs1>;
 	status = "disabled";
 };
 
@@ -272,7 +272,7 @@
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio2 26 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_spi_cs2>;
+	pinctrl-0 = <&pinctrl_ecspi2_t1 &pinctrl_spi_cs2>;
 	status = "disabled";
 };
 
@@ -294,7 +294,7 @@
 
 &flexcan1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan1_3>;
+	pinctrl-0 = <&pinctrl_flexcan1_t1>;
 	status = "disabled";
 };
 
@@ -421,6 +421,49 @@
 #define PAD_CTRL_NO 0x80000000
 
 &iomuxc {
+	audmux {
+
+		pinctrl_audmux_t1: audmux-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
+				MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x130b0
+				MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+				MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
+			>;
+		};
+	};
+
+	ecspi1 {
+
+		pinctrl_ecspi1_t1: ecspi1grp-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
+				MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
+				MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
+			>;
+		};
+	};
+
+	ecspi2 {
+		pinctrl_ecspi2_t1: ecspi2grp-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
+				MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
+				MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
+			>;
+		};
+	};
+
+	flexcan1 {
+
+		pinctrl_flexcan1_t1: flexcan1grp-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
+				MX6QDL_PAD_GPIO_8__FLEXCAN1_RX   0x80000000
+			>;
+		};
+	};
+
 	imx6q-apalis {
 		pinctrl_apalis_gpio1: apalis_gpio1-1 {
 			fsl,pins = <
@@ -526,6 +569,151 @@
 			>;
 		};
 	};
+
+	ipu1 {
+
+		pinctrl_ipu1_t1: ipu1grp-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK	0x61
+				MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15	0x61                /* DE */
+				MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02	0x61                /* HSync */
+				MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03	0x61                /* VSync */
+				MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00	0x61
+				MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01	0x61
+				MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02	0x61
+				MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03	0x61
+				MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04	0x61
+				MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05	0x61
+				MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06	0x61
+				MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07	0x61
+				MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08	0x61
+				MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09	0x61
+				MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10	0x61
+				MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11	0x61
+				MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12	0x61
+				MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13	0x61
+				MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14	0x61
+				MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15	0x61
+				MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16	0x61
+				MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17	0x61
+				MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18	0x61
+				MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19	0x61
+				MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20	0x61
+				MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21	0x61
+				MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22	0x61
+				MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23	0x61
+			>;
+		};
+	};
+
+	ipu2 {
+
+		pinctrl_ipu2_t1: ipu2grp-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xD1
+				MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xD1
+				MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xD1
+				MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xD1
+				MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xF9
+				MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xF9
+				MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xF9
+				MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xF9
+				MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xF9
+				MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xF9
+				MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xF9
+				MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xF9
+				MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xF9
+				MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xF9
+				MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xF9
+				MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xF9
+				MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xF9
+				MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xF9
+				MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xF9
+				MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xF9
+			>;
+		};
+	};
+
+	uart1 {
+
+		pinctrl_uart1_t1: uart1grp-t1 { /* DTE mode */
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
+				MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
+				MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
+				MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart1_t2: uart1grp-t2 { /* Additional DTR, DSR, DCD */
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
+				MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
+				MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
+			>;
+		};
+	};
+
+	uart2 {
+
+		pinctrl_uart2_t1: uart2grp-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA   0x1b0b1
+				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA   0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2_t2: uart2grp-t2 { /* DTE mode */
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA   0x1b0b1
+				MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA   0x1b0b1
+				MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
+				MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
+			>;
+		};
+	};
+
+	uart4 {
+		pinctrl_uart4_t1: uart4grp-t1 { /* DTE mode */
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
+				MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
+			>;
+		};
+	};
+
+	uart5 {
+		pinctrl_uart5_t1: uart5grp-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+				MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+			>;
+		};
+		pinctrl_uart5_t2: uart5grp-t2 { /* DTE mode */
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
+				MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
+			>;
+		};
+	};
+
+	usdhc1 {
+
+		pinctrl_usdhc1_t1: usdhc1grp-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
+				MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
+				MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+				MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+				MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+				MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+				MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
+				MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
+				MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
+				MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
+			>;
+		};
+	};
 };
 
 &ldb {
@@ -573,10 +761,11 @@
 	status = "okay";
 };
 
+//#define USE_UART_IN_DTE_MODE /* on HW V1.1 */
 &uart1 {
 	pinctrl-names = "default";
-#if 0
-	pinctrl-0 = <&pinctrl_uart1_3>;
+#ifdef USE_UART_IN_DTE_MODE
+	pinctrl-0 = <&pinctrl_uart1_t1 &pinctrl_uart1_t2>;
 	fsl,dte-mode;
 	fsl,uart-has-rtscts;
 #else
@@ -587,27 +776,35 @@
 
 &uart2 {
 	pinctrl-names = "default";
-#if 0
-	pinctrl-0 = <&pinctrl_uart2_5>;
+#ifdef USE_UART_IN_DTE_MODE
+	pinctrl-0 = <&pinctrl_uart2_t2>;
 	fsl,dte-mode;
 	fsl,uart-has-rtscts;
 #else
-	pinctrl-0 = <&pinctrl_uart2_4>;
+	pinctrl-0 = <&pinctrl_uart2_t1>;
 #endif
 	status = "disabled";
 };
 
 &uart4 {
 	pinctrl-names = "default";
+#ifdef USE_UART_IN_DTE_MODE
+	pinctrl-0 = <&pinctrl_uart4_t1>;
+ 	fsl,dte-mode;
+#else
 	pinctrl-0 = <&pinctrl_uart4_1>;
-/* TODO 	fsl,dte-mode; */
+#endif
 	status = "disabled";
 };
 
 &uart5 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart5_1>;
-/* TODO 	fsl,dte-mode; */
+#ifdef USE_UART_IN_DTE_MODE
+	pinctrl-0 = <&pinctrl_uart5_t2>;
+ 	fsl,dte-mode;
+#else
+	pinctrl-0 = <&pinctrl_uart5_t1>;
+#endif
 	status = "disabled";
 };
 
@@ -628,7 +825,7 @@
 &usdhc1 {
 	label = "MMC1";
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1_2 &pinctrl_mmc_cd>;
+	pinctrl-0 = <&pinctrl_usdhc1_t1 &pinctrl_mmc_cd>;
 	cd-gpios = <&gpio4 20 0>;
 	vmmc-supply = <&reg_3p3v>;
 	bus-width = <8>;
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index 17956eb5526e..66b2156b660f 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -57,7 +57,7 @@
 		disp_id = <0>;
 		default_ifmt = "RGB666";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ipu1_6>;
+		pinctrl-0 = <&pinctrl_ipu1_t1>;
 		status = "disabled";
 	};
 
@@ -155,7 +155,7 @@
 		model = "imx-spdif";
 		spdif-controller = <&spdif>;
 		spdif-out;
-		spdif-in;
+		/* spdif-in; */
 		status = "disabled";
 	};
 
@@ -167,7 +167,7 @@
 
 &audmux {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_audmux_5 &pinctrl_audmux_mclk_2 &pinctrl_mic_gnd>;
+	pinctrl-0 = <&pinctrl_audmux_t1 &pinctrl_audmux_mclk_2 &pinctrl_mic_gnd>;
 	status = "okay";
 };
 
@@ -176,13 +176,13 @@
 	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio5 2 0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_spi_cs1>;
+	pinctrl-0 = <&pinctrl_ecspi4_t1 &pinctrl_spi_cs1>;
 	status = "disabled";
 };
 
 &fec {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet_5>;
+	pinctrl-0 = <&pinctrl_enet_t1>;
 	phy-mode = "rmii";
 	status = "okay";
 };
@@ -190,7 +190,7 @@
 /* Colibri SDDIMM 55/63 */
 &flexcan1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan1_3>;
+	pinctrl-0 = <&pinctrl_flexcan1_t1>;
 	status = "disabled";
 };
 
@@ -302,8 +302,96 @@
 #define PAD_CTRL_IN 0x0040 /*( PAD_CTL_SPEED_LOW )*/
 #define PAD_CTRL_NO 0x80000000
 
-//TODO
 &iomuxc {
+	audmux {
+
+		pinctrl_audmux_t1: audmux-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL0__AUD5_TXC  0x130b0
+				MX6QDL_PAD_KEY_ROW0__AUD5_TXD  0x130b0
+				MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
+				MX6QDL_PAD_KEY_ROW1__AUD5_RXD  0x130b0
+			>;
+		};
+	};
+
+	csi {
+		/* CSI pins used as GPIO */
+		pinctrl_csi_gpio_1: csi_gpio-1 {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_A24__GPIO5_IO04   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_SD2_CMD__GPIO1_IO11   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_D18__GPIO3_IO18   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_A19__GPIO2_IO19   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_D29__GPIO3_IO29   PAD_CTRL_HYS_PD
+				MX6QDL_PAD_EIM_A23__GPIO6_IO06   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_A20__GPIO2_IO18   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_A17__GPIO2_IO21   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_A18__GPIO2_IO20   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_EB3__GPIO2_IO31   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_D17__GPIO3_IO17   PAD_CTRL_HYS_PU
+				MX6QDL_PAD_SD2_DAT0__GPIO1_IO15  PAD_CTRL_HYS_PU
+			>;
+		};
+	};
+
+	ecspi4 {
+		pinctrl_ecspi4_t1: ecspi4grp-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+				MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+				MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+			>;
+		};
+	};
+
+	enet {
+
+		pinctrl_enet_t1: enetgrp-t1 { /* RMII */
+			fsl,pins = <
+				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+				MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+				MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+				MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
+				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+				MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
+				MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
+				MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	((1<<30) | 0x1b0b0)
+			>;
+		};
+	};
+
+	flexcan1 {
+
+		pinctrl_flexcan1_t1: flexcan1grp-t1 {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
+				MX6QDL_PAD_GPIO_8__FLEXCAN1_RX   0x80000000
+			>;
+		};
+	};
+
+	gpio {
+		pinctrl_gpio_1: gpio-1 {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_7__GPIO1_IO07       PAD_CTRL_HYS_PU
+				MX6QDL_PAD_GPIO_8__GPIO1_IO08       PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_D26__GPIO3_IO26      PAD_CTRL_HYS_PU
+				MX6QDL_PAD_EIM_D27__GPIO3_IO27      PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_D6__GPIO2_IO06     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_D3__GPIO2_IO03     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DI0_PIN4__GPIO4_IO20     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_SD4_DAT3__GPIO2_IO11     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_NANDF_D4__GPIO2_IO04     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_SD4_DAT0__GPIO2_IO08     PAD_CTRL_HYS_PU
+			>;
+		};
+	};
+
 	imx6dl-colibri {
 		pinctrl_audmux_mclk_2: audmux_mclk-2 {
 			fsl,pins = <
@@ -382,43 +470,88 @@
 			>;
 		};
 	};
-	csi {
-		/* CSI pins used as GPIO */
-		pinctrl_csi_gpio_1: csi_gpio-1 {
+
+	ipu1 {
+
+		pinctrl_ipu1_t1: ipu1grp-t1 {
 			fsl,pins = <
-				MX6QDL_PAD_EIM_A24__GPIO5_IO04   PAD_CTRL_HYS_PU
-				MX6QDL_PAD_SD2_CMD__GPIO1_IO11   PAD_CTRL_HYS_PU
-				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 PAD_CTRL_HYS_PU
-				MX6QDL_PAD_EIM_D18__GPIO3_IO18   PAD_CTRL_HYS_PU
-				MX6QDL_PAD_EIM_A19__GPIO2_IO19   PAD_CTRL_HYS_PU
-				MX6QDL_PAD_EIM_D29__GPIO3_IO29   PAD_CTRL_HYS_PD
-				MX6QDL_PAD_EIM_A23__GPIO6_IO06   PAD_CTRL_HYS_PU
-				MX6QDL_PAD_EIM_A20__GPIO2_IO18   PAD_CTRL_HYS_PU
-				MX6QDL_PAD_EIM_A17__GPIO2_IO21   PAD_CTRL_HYS_PU
-				MX6QDL_PAD_EIM_A18__GPIO2_IO20   PAD_CTRL_HYS_PU
-				MX6QDL_PAD_EIM_EB3__GPIO2_IO31   PAD_CTRL_HYS_PU
-				MX6QDL_PAD_EIM_D17__GPIO3_IO17   PAD_CTRL_HYS_PU
-				MX6QDL_PAD_SD2_DAT0__GPIO1_IO15  PAD_CTRL_HYS_PU
+				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
+				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
+				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
+				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
+				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
+				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
+				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
+				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
+				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
+				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
+				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
+				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
+				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
+				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
+				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
+				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
+				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
+				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
+				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
+				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
+				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 			>;
 		};
 	};
-	gpio {
-		pinctrl_gpio_1: gpio-1 {
+
+	spdif {
+
+		pinctrl_spdif_t1: spdifgrp-t1 {
 			fsl,pins = <
-				MX6QDL_PAD_GPIO_7__GPIO1_IO07       PAD_CTRL_HYS_PU
-				MX6QDL_PAD_GPIO_8__GPIO1_IO08       PAD_CTRL_HYS_PU
-				MX6QDL_PAD_EIM_D26__GPIO3_IO26      PAD_CTRL_HYS_PU
-				MX6QDL_PAD_EIM_D27__GPIO3_IO27      PAD_CTRL_HYS_PU
-				MX6QDL_PAD_NANDF_D6__GPIO2_IO06     PAD_CTRL_HYS_PU
-				MX6QDL_PAD_NANDF_D3__GPIO2_IO03     PAD_CTRL_HYS_PU
-				MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 PAD_CTRL_HYS_PU
-				MX6QDL_PAD_DI0_PIN4__GPIO4_IO20     PAD_CTRL_HYS_PU
-				MX6QDL_PAD_SD4_DAT3__GPIO2_IO11     PAD_CTRL_HYS_PU
-				MX6QDL_PAD_NANDF_D4__GPIO2_IO04     PAD_CTRL_HYS_PU
-				MX6QDL_PAD_SD4_DAT0__GPIO2_IO08     PAD_CTRL_HYS_PU
+				MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+			>;
+		};
+	};
+
+	uart1 {
+
+		pinctrl_uart1_t1: uart1grp-t1 { /* DTE mode */
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
+				MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
+				MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
+				MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart1_t2: uart1grp-t2 { /* Additional DTR, DSR, DCD */
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
+				MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
+				MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 			>;
 		};
 	};
+
+	uart2 {
+
+		pinctrl_uart2_t1: uart2grp-t1 { /* DTE mode */
+			fsl,pins = <
+				MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA   0x1b0b1
+				MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA   0x1b0b1
+				MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
+				MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
+			>;
+		};
+	};
+
+	uart3 {
+
+		pinctrl_uart3_t1: uart3grp-t1 { /* DTE mode */
+			fsl,pins = <
+				MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
+				MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
+			>;
+		};
+	};
+
 	weim {
 		pinctrl_weim_cs1_1: weim_cs1grp-1 {
 			fsl,pins = <
@@ -580,7 +713,7 @@
 /* S/PDIF out on SODIMM137 */
 &spdif {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_spdif_3>;
+	pinctrl-0 = <&pinctrl_spdif_t1>;
 	status = "disabled";
 };
 
@@ -592,18 +725,16 @@
 /* UART A */
 &uart1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1_3 &pinctrl_uart1_4>;
-#if 1
+	pinctrl-0 = <&pinctrl_uart1_t1 &pinctrl_uart1_t1>;
 	fsl,dte-mode;
 	fsl,uart-has-rtscts;
-#endif
 	status = "disabled";
 };
 
 /* UART B */
 &uart2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2_5>;
+	pinctrl-0 = <&pinctrl_uart2_t1>;
 	fsl,dte-mode;
 	fsl,uart-has-rtscts;
 	status = "disabled";
@@ -612,7 +743,7 @@
 /* UART_C */
 &uart3 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart3_4>;
+	pinctrl-0 = <&pinctrl_uart3_t1>;
 	fsl,dte-mode;
 	status = "disabled";
 };
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 40c88fa69b53..2e9879f2b65f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -646,7 +646,7 @@
 				#size-cells = <1>;
 				ranges = <0 0x020cc000 0x4000>;
 
-				snvs_rtc: snvs-rtc-lp@34 {
+				snvs-rtc-lp@34 {
 					compatible = "fsl,sec-v4.0-mon-rtc-lp";
 					reg = <0x34 0x58>;
 					interrupts = <0 19 0x04 0 20 0x04>;
@@ -1069,24 +1069,6 @@
 				MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x130b0
 			>;
 		};
-
-		pinctrl_audmux_4: audmux-4 {
-			fsl,pins = <
-				MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
-				MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x130b0
-				MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
-				MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
-			>;
-		};
-
-		pinctrl_audmux_5: audmux-5 {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_COL0__AUD5_TXC  0x130b0
-				MX6QDL_PAD_KEY_ROW0__AUD5_TXD  0x130b0
-				MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
-				MX6QDL_PAD_KEY_ROW1__AUD5_RXD  0x130b0
-			>;
-		};
 	};
 
 	ecspi1 {
@@ -1111,23 +1093,6 @@
 				MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
 			>;
 		};
-		pinctrl_ecspi1_3: ecspi1grp-3 {
-			fsl,pins = <
-				MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
-				MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
-				MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
-			>;
-		};
-	};
-
-	ecspi2 {
-		pinctrl_ecspi2_1: ecspi2grp-1 {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
-				MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
-				MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
-			>;
-		};
 	};
 
 	ecspi3 {
@@ -1140,16 +1105,6 @@
 		};
 	};
 
-	ecspi4 {
-		pinctrl_ecspi4_1: ecspi4grp-1 {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
-				MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
-				MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
-			>;
-		};
-	};
-
 	enet {
 		pinctrl_enet_1: enetgrp-1 {
 			fsl,pins = <
@@ -1234,21 +1189,6 @@
 			>;
 		};
 
-		/* RMII */
-		pinctrl_enet_5: enetgrp-5 {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
-				MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
-				MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
-				MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
-				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
-				MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
-				MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
-				MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
-				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	((1<<30) | 0x1b0b0)
-			>;
-		};
 	};
 
 	esai {
@@ -1296,12 +1236,6 @@
 				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
 			>;
 		};
-		pinctrl_flexcan1_3: flexcan1grp-3 {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
-				MX6QDL_PAD_GPIO_8__FLEXCAN1_RX   0x80000000
-			>;
-		};
 	};
 
 	flexcan2 {
@@ -1552,65 +1486,6 @@
 			>;
 		};
 
-		pinctrl_ipu1_5: ipu1grp-5 {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK	0x61
-				MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15	0x61                /* DE */
-				MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02	0x61                /* HSync */
-				MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03	0x61                /* VSync */
-				MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00	0x61
-				MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01	0x61
-				MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02	0x61
-				MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03	0x61
-				MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04	0x61
-				MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05	0x61
-				MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06	0x61
-				MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07	0x61
-				MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08	0x61
-				MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09	0x61
-				MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10	0x61
-				MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11	0x61
-				MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12	0x61
-				MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13	0x61
-				MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14	0x61
-				MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15	0x61
-				MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16	0x61
-				MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17	0x61
-				MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18	0x61
-				MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19	0x61
-				MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20	0x61
-				MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21	0x61
-				MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22	0x61
-				MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23	0x61
-			>;
-		};
-
-		pinctrl_ipu1_6: ipu1grp-6 {
-			fsl,pins = <
-				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
-				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
-				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
-				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
-				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
-				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
-				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
-				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
-				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
-				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
-				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
-				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
-				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
-				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
-				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
-				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
-				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
-				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
-				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
-				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
-				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
-				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
-			>;
-		};
 	};
 
 	mlb {
@@ -1706,12 +1581,6 @@
 				MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 			>;
 		};
-
-		pinctrl_spdif_3: spdifgrp-3 {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
-			>;
-		};
 	};
 
 	uart1 {
@@ -1728,23 +1597,6 @@
 				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
 			>;
 		};
-
-		pinctrl_uart1_3: uart1grp-3 { /* DTE mode */
-			fsl,pins = <
-				MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
-				MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
-				MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
-				MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
-			>;
-		};
-
-		pinctrl_uart1_4: uart1grp-4 { /* Additional DTR, DSR, DCD */
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
-				MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
-				MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
-			>;
-		};
 	};
 
 	uart2 {
@@ -1763,31 +1615,6 @@
 				MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
 			>;
 		};
-
-		pinctrl_uart2_3: uart2grp-3 {
-			fsl,pins = <
-				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA   0x1b0b1
-				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA   0x1b0b1
-				MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
-				MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
-			>;
-		};
-
-		pinctrl_uart2_4: uart2grp-4 {
-			fsl,pins = <
-				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA   0x1b0b1
-				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA   0x1b0b1
-			>;
-		};
-
-		pinctrl_uart2_5: uart2grp-5 { /* DTE mode */
-			fsl,pins = <
-				MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA   0x1b0b1
-				MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA   0x1b0b1
-				MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
-				MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
-			>;
-		};
 	};
 
 	uart3 {
@@ -1799,7 +1626,6 @@
 				MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
 			>;
 		};
-
 		pinctrl_uart3_2: uart3grp-2 {
 			fsl,pins = <
 				MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
@@ -1808,19 +1634,6 @@
 				MX6QDL_PAD_EIM_D31__UART3_RTS_B   0x1b0b1
 			>;
 		};
-
-		pinctrl_uart3_3: uart3grp-3 {
-			fsl,pins = <
-				MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
-				MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
-			>;
-		};
-		pinctrl_uart3_4: uart3grp-4 { /* DTE mode */
-			fsl,pins = <
-				MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
-				MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
-			>;
-		};
 	};
 
 	uart4 {
@@ -1832,15 +1645,6 @@
 		};
 	};
 
-	uart5 {
-		pinctrl_uart5_1: uart5grp-1 {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
-				MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
-			>;
-		};
-	};
-
 	usbotg {
 		pinctrl_usbotg_1: usbotggrp-1 {
 			fsl,pins = <
@@ -1896,20 +1700,6 @@
 				MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
 			>;
 		};
-		pinctrl_usdhc1_2: usdhc1grp-2 {
-			fsl,pins = <
-				MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
-				MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
-				MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
-				MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
-				MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
-				MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
-				MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
-				MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
-				MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
-				MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
-			>;
-		};
 	};
 
 	usdhc2 {