diff options
| author | Adrian Alonso <aalonso@freescale.com> | 2015-04-09 15:06:58 -0500 |
|---|---|---|
| committer | guoyin.chen <guoyin.chen@freescale.com> | 2015-05-08 17:26:24 +0800 |
| commit | 151a9c1dcfd60ddfb61e3f097642f96b54983e9c (patch) | |
| tree | 409544cef26a7ce466341461cc4742e78d69d9fe | |
| parent | f5bf551d0f96e80bcf2a4ae42bebed7e0b54c0f5 (diff) | |
MLK-10615: ARM: imx7d: uart: set clock parents from dts
* Use devicetree clock bindings to set clock parent for UARTx_ROOT_CLKs
* Remove fixed configuration from MSL clk-imx7ds.c to be able to override
settings via dts.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
(cherry picked from commit 8f58af213283d1e98a16c9b27d69f8d97953bdaf)
| -rw-r--r-- | arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx7d-19x19-ddr3-arm2.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx7d-sdb.dts | 6 | ||||
| -rw-r--r-- | arch/arm/mach-imx/clk-imx7d.c | 8 |
4 files changed, 14 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts index 57d3ef6f4d98..db3f5d285f5c 100644 --- a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts +++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts @@ -332,6 +332,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; status = "okay"; }; @@ -339,6 +341,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_1>; fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; status = "okay"; /* for DTE mode, add below change */ /* fsl,dte-mode;*/ diff --git a/arch/arm/boot/dts/imx7d-19x19-ddr3-arm2.dts b/arch/arm/boot/dts/imx7d-19x19-ddr3-arm2.dts index 4c3ccfea76c9..2442024263a8 100644 --- a/arch/arm/boot/dts/imx7d-19x19-ddr3-arm2.dts +++ b/arch/arm/boot/dts/imx7d-19x19-ddr3-arm2.dts @@ -217,6 +217,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; status = "okay"; }; @@ -224,6 +226,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_1>; fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; status = "okay"; /* for DTE mode, add below change */ /* fsl,dte-mode;*/ diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index dc6f2785c91d..2cdc384c0390 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -859,12 +859,16 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; status = "okay"; }; &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; fsl,uart-has-rtscts; status = "okay"; }; @@ -872,6 +876,8 @@ &uart6 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; fsl,uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/mach-imx/clk-imx7d.c b/arch/arm/mach-imx/clk-imx7d.c index 42e0e9ef0a81..e2f79613d3e5 100644 --- a/arch/arm/mach-imx/clk-imx7d.c +++ b/arch/arm/mach-imx/clk-imx7d.c @@ -905,14 +905,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) /* set uart module clock's parent clock source that must be great then 80Mhz */ if (uart_from_osc) imx_clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); - else - imx_clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_parent(clks[IMX7D_UART2_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_parent(clks[IMX7D_UART3_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_parent(clks[IMX7D_UART4_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_parent(clks[IMX7D_UART7_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); /* set pcie root's parent clk source */ imx_clk_set_parent(clks[IMX7D_PCIE_CTRL_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]); |