diff options
| author | Anson Huang <b20788@freescale.com> | 2015-04-20 11:25:54 +0800 |
|---|---|---|
| committer | guoyin.chen <guoyin.chen@freescale.com> | 2015-05-08 17:26:43 +0800 |
| commit | 8c285bf9aaf4ed763138bd410312ab3402e296d3 (patch) | |
| tree | 3aa96ce5c0fb6fcfe5c23386b32964bc492a2287 | |
| parent | dde08607700570a887465f9a192974e880bb808f (diff) | |
MLK-10699 ARM: imx: correct ahb clk parent select
Design team change the ahb's clk parent options but
did NOT update the DOC accordingly in time, so the
AHB/IPG's clk rate in clk tree is incorrect, AHB is
67.5MHz and IPG is 33.75MHz, but using scope to
monitor them, they are actually 135MHz and 67.5MHz,
update the clk parent option to make clk tree info
correct.
Signed-off-by: Anson Huang <b20788@freescale.com>
| -rw-r--r-- | arch/arm/mach-imx/clk-imx7d.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/clk-imx7d.c b/arch/arm/mach-imx/clk-imx7d.c index e2f79613d3e5..5313bed12ce4 100644 --- a/arch/arm/mach-imx/clk-imx7d.c +++ b/arch/arm/mach-imx/clk-imx7d.c @@ -57,9 +57,9 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk", "pll_audio_post_div", }; -static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_135m_clk", +static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk", "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", - "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div", + "pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div", "pll_video_post_div", }; static const char *dram_phym_sel[] = { "pll_dram_main_clk", |