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authorRoger Quadros <rogerq@ti.com>2014-09-02 16:57:07 +0300
committerTony Lindgren <tony@atomide.com>2014-09-04 12:39:29 -0700
commit331bbb595ef93b68272e011f8ac81b260e672db5 (patch)
treee8b18a51cb2626d3db8abb8312ccc80f333d9202
parent2b54057c9b2638792bdd83b58bad7a0cdf5f4533 (diff)
ARM: dts: am43x-epos-evm: Disable QSPI to prevent conflict with GPMC-NAND
Both QSPI and GPMC-NAND share the same Pin (A8) from the SoC for Chip Select functionality. So both can't be enabled simultaneously. Disable QSPI node to prevent the pin conflict as well as be similar to 3.12 release. CC: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Pekon Gupta <pekon@pek-sem.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index b489b278f184..ac3e4859935f 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -435,7 +435,7 @@
};
&gpmc {
- status = "okay";
+ status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
@@ -556,7 +556,7 @@
};
&qspi {
- status = "okay";
+ status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
pinctrl-names = "default";
pinctrl-0 = <&qspi1_default>;