diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2014-04-29 09:06:33 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan@agner.ch> | 2014-05-15 14:01:06 +0200 |
| commit | c0863bd749479578d343eb8a33df2ffc649d2113 (patch) | |
| tree | 60aaa1e504d0bc7c68ab21e84c4b39534ad0069c | |
| parent | 2d8f62e795944ddc719623028484b28354ba185d (diff) | |
fsl_nfc: add chip select
Add correct chip select handling. This is required when using
mainline U-Boot since chip select is properly done there as well.
| -rw-r--r-- | drivers/mtd/nand/fsl_nfc.c | 39 |
1 files changed, 10 insertions, 29 deletions
diff --git a/drivers/mtd/nand/fsl_nfc.c b/drivers/mtd/nand/fsl_nfc.c index 5f95b46b1a30..a925e416ea43 100644 --- a/drivers/mtd/nand/fsl_nfc.c +++ b/drivers/mtd/nand/fsl_nfc.c @@ -352,39 +352,20 @@ fsl_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) CONFIG_PAGE_CNT_SHIFT, 0x1); } -/* Control chips select signal on m54418twr board */ static void nfc_select_chip(struct mtd_info *mtd, int chip) { -#ifdef CONFIG_COLDFIRE - if (chip < 0) { - MCF_GPIO_PAR_FBCTL &= (MCF_GPIO_PAR_FBCTL_ALE_MASK & - MCF_GPIO_PAR_FBCTL_TA_MASK); - MCF_GPIO_PAR_FBCTL |= MCF_GPIO_PAR_FBCTL_ALE_FB_TS | - MCF_GPIO_PAR_FBCTL_TA_TA; - - MCF_GPIO_PAR_BE = - MCF_GPIO_PAR_BE_BE3_BE3 | MCF_GPIO_PAR_BE_BE2_BE2 | - MCF_GPIO_PAR_BE_BE1_BE1 | MCF_GPIO_PAR_BE_BE0_BE0; - - MCF_GPIO_PAR_CS &= ~MCF_GPIO_PAR_CS_CS1_NFC_CE; - MCF_GPIO_PAR_CS |= MCF_GPIO_PAR_CS_CS0_CS0; - return; - } + nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_CHIP_SEL_RB_MASK, + ROW_ADDR_CHIP_SEL_RB_SHIFT, 1); - MCF_GPIO_PAR_FBCTL &= (MCF_GPIO_PAR_FBCTL_ALE_MASK & - MCF_GPIO_PAR_FBCTL_TA_MASK); - MCF_GPIO_PAR_FBCTL |= MCF_GPIO_PAR_FBCTL_ALE_FB_ALE | - MCF_GPIO_PAR_FBCTL_TA_NFC_RB; - MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_BE3_FB_A1 | - MCF_GPIO_PAR_BE_BE2_FB_A0 | - MCF_GPIO_PAR_BE_BE1_BE1 | MCF_GPIO_PAR_BE_BE0_BE0; - - MCF_GPIO_PAR_CS &= (MCF_GPIO_PAR_BE_BE3_MASK & - MCF_GPIO_PAR_BE_BE2_MASK); - MCF_GPIO_PAR_CS |= MCF_GPIO_PAR_CS_CS1_NFC_CE; - return; -#endif + if (chip == 0) + nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_CHIP_SEL_MASK, + ROW_ADDR_CHIP_SEL_SHIFT, 1); + else if (chip == 1) + nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_CHIP_SEL_MASK, + ROW_ADDR_CHIP_SEL_SHIFT, 2); + else + nfc_clear(mtd, NFC_ROW_ADDR, ROW_ADDR_CHIP_SEL_MASK); } /* Read NAND Ready/Busy signal */ |