diff options
| author | Stephen Hemminger <shemminger@osdl.org> | 2006-12-04 17:08:19 -0800 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2006-12-07 04:58:33 -0500 |
| commit | c3905bc4b71ab562acf69765e8c4778bd263b9db (patch) | |
| tree | 95010fa74bf41e03efa907589d740416838af2b5 | |
| parent | 6771290102c4703dae56bc3e121deb63530e206c (diff) | |
[PATCH] sky2: receive queue watermark tweak
This patch makes the receive performance on some systems go from
714MB/s to 941MB/s. It adjusts the watermark of the receive queue
to be lower, thereby avoiding excess hardware flow control. This is
most important on the systems which have little/no additional buffering.
Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
| -rw-r--r-- | drivers/net/sky2.c | 11 | ||||
| -rw-r--r-- | drivers/net/sky2.h | 1 |
2 files changed, 9 insertions, 3 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index b9f7eb5453f1..a8e096393a41 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c @@ -1062,11 +1062,16 @@ static int sky2_rx_start(struct sky2_port *sky2) sky2->rx_put = sky2->rx_next = 0; sky2_qset(hw, rxq); + /* On PCI express lowering the watermark gives better performance */ + if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) + sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); + + /* These chips have no ram buffer? + * MAC Rx RAM Read is controlled by hardware */ if (hw->chip_id == CHIP_ID_YUKON_EC_U && - (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) { - /* MAC Rx RAM Read is controlled by hardware */ + (hw->chip_rev == CHIP_REV_YU_EC_U_A1 + || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); - } sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index 7760545edbf2..a63f6057b2ea 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h @@ -680,6 +680,7 @@ enum { BMU_FIFO_ENA | BMU_OP_ON, BMU_WM_DEFAULT = 0x600, + BMU_WM_PEX = 0x80, }; /* Tx BMU Control / Status Registers (Yukon-2) */ |