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authorFabio Estevam <fabio.estevam@freescale.com>2015-01-08 19:17:05 -0200
committerJason Liu <r64343@freescale.com>2015-02-02 14:47:20 +0800
commit245bf82e27c46db4f25e58634860f407b4c05309 (patch)
treee2eae93340278cd09e6ad98380a45632631f7181
parent96391f1b6535f8856149ebd8632c72e4561efdcf (diff)
MLK-10080 serial: imx: Fix imx_flush_buffer()
When running an userspace program that does a 'tcflush(fd, TCIOFLUSH)' call we still see the last received character in the URXD register afterwards. Clear UCR2_SRST bit so that the FIFO is flushed properly. Since UCR2_SRST also resets some UART registers, we need to save and restore some of them. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> (cherry picked from commit 87a72b6a6367a714026d5f38207301e7f53b0aca)
-rw-r--r--drivers/tty/serial/imx.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 94aba1dae198..42128dc69573 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -1383,12 +1383,38 @@ static void imx_shutdown(struct uart_port *port)
static void imx_flush_buffer(struct uart_port *port)
{
+ int i, temp;
struct imx_port *sport = (struct imx_port *)port;
if (sport->dma_is_enabled) {
sport->tx_bytes = 0;
dmaengine_terminate_all(sport->dma_chan_tx);
}
+
+ /*
+ * UCR2_SRST will reset the transmit and receive state machines,
+ * all FIFOs and register UBIR, UBMR, UBRC,
+ * and UTS[6-3], so save the required registers
+ */
+ sport->saved_reg[0] = readl(sport->port.membase + UBIR);
+ sport->saved_reg[1] = readl(sport->port.membase + UBMR);
+ sport->saved_reg[2] = readl(sport->port.membase + UBRC);
+ sport->saved_reg[3] = readl(sport->port.membase + IMX21_UTS);
+
+ i = 100;
+
+ temp = readl(sport->port.membase + UCR2);
+ temp &= ~UCR2_SRST;
+ writel(temp, sport->port.membase + UCR2);
+
+ while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
+ udelay(1);
+
+ /* Restore the registers */
+ writel(sport->saved_reg[0], sport->port.membase + UBIR);
+ writel(sport->saved_reg[1], sport->port.membase + UBMR);
+ writel(sport->saved_reg[2], sport->port.membase + UBRC);
+ writel(sport->saved_reg[3], sport->port.membase + IMX21_UTS);
}
static void