MLK-10723-1 mxc IPUv3: Remove some unused IPU deblock register bases

The driver doesn't have functional support for IPU_DISP0/1_BASE,
IPU_ISP_REG_BASE, IPU_DP_REG_BASE, IPU_IRT_REG_BASE, IPU_LUT_REG_BASE,
and IPU_ISP_TBPR_REG_BASE.  Let's remove them to save some lines.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>

5 files changed, 2 insertions, 26 deletions

diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
index 8b91a29c8795..d8a280dbcd3e 100644
--- a/drivers/mxc/ipu3/ipu_common.c
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -424,14 +424,11 @@ static int ipu_probe(struct platform_device *pdev)
 				ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K);
 	ipu->vdi_reg = devm_ioremap(&pdev->dev,
 				ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE);
-	ipu->disp_base[1] = devm_ioremap(&pdev->dev,
-				ipu_base + IPU_DISP1_BASE, SZ_4K);
 	if (!ipu->cm_reg || !ipu->ic_reg || !ipu->idmac_reg ||
 		!ipu->dp_reg || !ipu->dc_reg || !ipu->dmfc_reg ||
 		!ipu->di_reg[0] || !ipu->di_reg[1] || !ipu->smfc_reg ||
 		!ipu->csi_reg[0] || !ipu->csi_reg[1] || !ipu->cpmem_base ||
-		!ipu->tpmem_base || !ipu->dc_tmpl_reg || !ipu->disp_base[1]
-		|| !ipu->vdi_reg)
+		!ipu->tpmem_base || !ipu->dc_tmpl_reg || !ipu->vdi_reg)
 		return -ENOMEM;
 
 	dev_dbg(ipu->dev, "IPU CM Regs = %p\n", ipu->cm_reg);
@@ -448,7 +445,6 @@ static int ipu_probe(struct platform_device *pdev)
 	dev_dbg(ipu->dev, "IPU CPMem = %p\n", ipu->cpmem_base);
 	dev_dbg(ipu->dev, "IPU TPMem = %p\n", ipu->tpmem_base);
 	dev_dbg(ipu->dev, "IPU DC Template Mem = %p\n", ipu->dc_tmpl_reg);
-	dev_dbg(ipu->dev, "IPU Display Region 1 Mem = %p\n", ipu->disp_base[1]);
 	dev_dbg(ipu->dev, "IPU VDI Regs = %p\n", ipu->vdi_reg);
 
 	ipu->ipu_clk = devm_clk_get(ipu->dev, "bus");
diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c
index f1719208d95a..90668cf8e3f2 100644
--- a/drivers/mxc/ipu3/ipu_disp.c
+++ b/drivers/mxc/ipu3/ipu_disp.c
@@ -1932,15 +1932,6 @@ int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
 }
 EXPORT_SYMBOL(ipu_disp_get_window_pos);
 
-void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset)
-{
-	if (channel == DIRECT_ASYNC0)
-		writel(value, ipu->disp_base[0] + offset);
-	else if (channel == DIRECT_ASYNC1)
-		writel(value, ipu->disp_base[1] + offset);
-}
-EXPORT_SYMBOL(ipu_disp_direct_write);
-
 void ipu_reset_disp_panel(struct ipu_soc *ipu)
 {
 	uint32_t tmp;
diff --git a/drivers/mxc/ipu3/ipu_prv.h b/drivers/mxc/ipu3/ipu_prv.h
index 6c6ea3a909f1..8c027f43db44 100644
--- a/drivers/mxc/ipu3/ipu_prv.h
+++ b/drivers/mxc/ipu3/ipu_prv.h
@@ -94,7 +94,6 @@ struct ipu_soc {
 	void __iomem *csi_reg[2];
 	void __iomem *cpmem_base;
 	void __iomem *tpmem_base;
-	void __iomem *disp_base[2];
 	void __iomem *vdi_reg;
 
 	struct device *dev;
diff --git a/drivers/mxc/ipu3/ipu_regs.h b/drivers/mxc/ipu3/ipu_regs.h
index 8a424ee6b2c7..9330057295a3 100644
--- a/drivers/mxc/ipu3/ipu_regs.h
+++ b/drivers/mxc/ipu3/ipu_regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2005-2015 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -37,21 +37,14 @@ extern int g_ipu_hw_rev;
 #define IPU_MAX_VDI_IN_WIDTH	({g_ipu_hw_rev >= 3 ? \
 				   (968) : \
 				   (720); })
-#define IPU_DISP0_BASE		0x00000000
 #define IPU_MCU_T_DEFAULT	8
-#define IPU_DISP1_BASE		({g_ipu_hw_rev < 4 ? \
-				(IPU_MCU_T_DEFAULT << 25) : \
-				(0x00000000); })
 #define IPUV3DEX_REG_BASE	0x1E000000
 #define IPUV3M_REG_BASE		0x06000000
 #define IPUV3H_REG_BASE		0x00200000
 
 #define IPU_CM_REG_BASE		0x00000000
 #define IPU_IDMAC_REG_BASE	0x00008000
-#define IPU_ISP_REG_BASE	0x00010000
-#define IPU_DP_REG_BASE		0x00018000
 #define IPU_IC_REG_BASE		0x00020000
-#define IPU_IRT_REG_BASE	0x00028000
 #define IPU_CSI0_REG_BASE	0x00030000
 #define IPU_CSI1_REG_BASE	0x00038000
 #define IPU_DI0_REG_BASE	0x00040000
@@ -63,7 +56,6 @@ extern int g_ipu_hw_rev;
 #define IPU_CPMEM_REG_BASE 	({g_ipu_hw_rev >= 4 ? \
 				   (0x00100000) : \
 				   (0x01000000); })
-#define IPU_LUT_REG_BASE	0x01020000
 #define IPU_SRM_REG_BASE 	({g_ipu_hw_rev >= 4 ? \
 				   (0x00140000) : \
 				   (0x01040000); })
@@ -73,7 +65,6 @@ extern int g_ipu_hw_rev;
 #define IPU_DC_TMPL_REG_BASE 	({g_ipu_hw_rev >= 4 ? \
 				   (0x00180000) : \
 				   (0x01080000); })
-#define IPU_ISP_TBPR_REG_BASE	0x010C0000
 
 /* Register addresses */
 /* IPU Common registers */
diff --git a/include/linux/ipu-v3.h b/include/linux/ipu-v3.h
index 6ae09fd8b210..ae09614a2257 100644
--- a/include/linux/ipu-v3.h
+++ b/include/linux/ipu-v3.h
@@ -706,7 +706,6 @@ int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel
 
 int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
 			 uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig);
-void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset);
 void ipu_reset_disp_panel(struct ipu_soc *ipu);
 
 /* CMOS Sensor Interface API */