diff options
| author | Robin Gong <yibin.gong@nxp.com> | 2016-02-02 16:30:50 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2016-05-23 14:56:04 -0500 |
| commit | 8b381036631a5704b4f1fab18ee7fe4184655523 (patch) | |
| tree | ff6a6e58125ea0b2b1d6caa11726276bcc552eb3 | |
| parent | 5db98a4109ac40418b9bb825fd2bbe916a80de20 (diff) | |
MLK-12371: ARM: imx: suspend-imx7: correct HW_ANADIG_SNVS_MISC_CTRL set
To avoid touch other bits of HW_ANADIG_SNVS_MISC_CTRL , use set/clear register
, and correct the bit29 setting:
--before: write 1 to toggle DDR power pin to high before enter DDR retention,
and write 1 again to pull pin to low when exit from DDR retention.
--now: write 1 to pull DDR power pin to high and write 0 to low.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
| -rw-r--r-- | arch/arm/mach-imx/suspend-imx7.S | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/suspend-imx7.S b/arch/arm/mach-imx/suspend-imx7.S index 7c85a64a8bb7..5f4e31152a69 100644 --- a/arch/arm/mach-imx/suspend-imx7.S +++ b/arch/arm/mach-imx/suspend-imx7.S @@ -81,6 +81,8 @@ #define GPC_PGC_C0 0x800 #define GPC_PGC_FM 0xa00 #define ANADIG_SNVS_MISC_CTRL 0x380 +#define ANADIG_SNVS_MISC_CTRL_SET 0x384 +#define ANADIG_SNVS_MISC_CTRL_CLR 0x388 #define ANADIG_DIGPROG 0x800 #define DDRC_STAT 0x4 #define DDRC_PWRCTL 0x30 @@ -336,11 +338,12 @@ ldr r7, [r11, r6] orr r7, r7, #0x1 str r7, [r11, r6] +11: /* turn off ddr power */ ldr r11, [r0, #PM_INFO_MX7_ANATOP_V_OFFSET] ldr r7, =(0x1 << 29) - str r7, [r11, #ANADIG_SNVS_MISC_CTRL] -11: + str r7, [r11, #ANADIG_SNVS_MISC_CTRL_SET] + ldr r11, [r0, #PM_INFO_MX7_SRC_V_OFFSET] ldr r6, =0x1000 ldr r7, [r11, r6] @@ -367,7 +370,7 @@ /* turn on ddr power */ ldr r7, =(0x1 << 29) - str r7, [r1, #ANADIG_SNVS_MISC_CTRL] + str r7, [r1, #ANADIG_SNVS_MISC_CTRL_CLR] ldr r6, =50 wait_delay @@ -419,7 +422,7 @@ str r7, [r11] 12: ldr r7, =(0x1 << 30) - str r7, [r1, #ANADIG_SNVS_MISC_CTRL] + str r7, [r1, #ANADIG_SNVS_MISC_CTRL_SET] /* need to delay ~5mS */ ldr r6, =0x100000 |