diff options
| author | Kenji Chen <kenjchen@nvidia.com> | 2011-03-09 10:44:16 +0800 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-03-09 19:06:19 -0800 |
| commit | c59573a1ef6311fb6e864a3c6d6e64adf4859c9c (patch) | |
| tree | 62bbb28aaad6df868acced6c6727367cf6a526f6 | |
| parent | 60944285f2490d3622b444c0a889b3fa33708aa3 (diff) | |
[ARM] tegra: pinmux: Correct driving strength programming offset
Offset of driving strength for DRVUP is 20 instead of 12.
Change-Id: If886a8604ea43f57a8ae11d3deabb022fb8d3efd
Reviewed-on: http://git-master/r/22133
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/pinmux.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index 027346cc8773..d94e348412f3 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -459,8 +459,8 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, spin_lock_irqsave(&mux_lock, flags); reg = pg_readl(drive_pingroups[pg].reg); - reg &= ~(0x1f << 12); - reg |= pull_up << 12; + reg &= ~(0x1f << 20); + reg |= pull_up << 20; pg_writel(reg, drive_pingroups[pg].reg); spin_unlock_irqrestore(&mux_lock, flags); |