diff options
author | Alex Frid <afrid@nvidia.com> | 2010-07-16 20:26:55 -0700 |
---|---|---|
committer | Gary King <gking@nvidia.com> | 2010-07-22 13:21:53 -0700 |
commit | a6c82d001633c15b1a1da366ba979c67ae1c5a48 (patch) | |
tree | ace549e19c43882cee3ec05da03dd89fe8db3187 | |
parent | 3fc337ed7b28466d3446bb183626581f33dfdc7c (diff) |
[ARM/tegra] ODM: Integrated Elpida EMC DVFS table.
Integrated Elpida EMC DVFS table for Whistler E1108 processor board.
Bug 709629
Change-Id: I493d2e8cb3f87b9bcabeee97602994d4d85c794e
Reviewed-on: http://git-master.nvidia.com/r/4106
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
-rw-r--r-- | arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c | 350 |
1 files changed, 350 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c index f798a7d4a703..6dbeba59b422 100644 --- a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c +++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c @@ -561,6 +561,334 @@ static const NvOdmSdramControllerConfigAdv s_NvOdmE1108HynixEmcConfigTable[] = } }; +static const NvOdmSdramControllerConfigAdv s_NvOdmE1108ElpidaEmcConfigTable[] = +{ + { + 0x20, /* Rev 2.0 */ + 18000, /* SDRAM frquency */ + 900, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000002, /* RC */ + 0x00000006, /* RFC */ + 0x00000003, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x00000038, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000003, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x0000004b, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xA06A04AE, /* CFG_DIG_DLL */ + 0x007FE010, /* DLL_XFORM_DQS */ + 0x00003010, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000002, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + 0x20, /* Rev 2.0 */ + 27000, /* SDRAM frquency */ + 950, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000002, /* RC */ + 0x00000006, /* RFC */ + 0x00000003, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x00000054, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000004, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000071, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xA06A04AE, /* CFG_DIG_DLL */ + 0x007FE010, /* DLL_XFORM_DQS */ + 0x00003010, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000003, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + 0x20, /* Rev 2.0 */ + 54000, /* SDRAM frquency */ + 1000, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000004, /* RC */ + 0x00000008, /* RFC */ + 0x00000003, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x000000a8, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000008, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x000000e1, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000000, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xA06A04AE, /* CFG_DIG_DLL */ + 0x007FE010, /* DLL_XFORM_DQS */ + 0x00003010, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000005, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + 0x20, /* Rev 2.0 */ + 108000, /* SDRAM frquency */ + 1000, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000007, /* RC */ + 0x0000000f, /* RFC */ + 0x00000005, /* RAS */ + 0x00000003, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x0000017f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000010, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x000001c2, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000001, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xA06A04AE, /* CFG_DIG_DLL */ + 0x007FE010, /* DLL_XFORM_DQS */ + 0x00003010, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x0000000a, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + 0x20, /* Rev 2.0 */ + 150000, /* SDRAM frquency */ + 1000, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000009, /* RC */ + 0x00000014, /* RFC */ + 0x00000007, /* RAS */ + 0x00000004, /* RP */ + 0x00000006, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x00000009, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000002, /* REXT */ + 0x00000002, /* WDV */ + 0x00000005, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000008, /* QSAFE */ + 0x0000000b, /* RDV */ + 0x0000021f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000004, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000a, /* RW2PDEN */ + 0x00000015, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000008, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000270, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000001, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000082, /* FBIO_CFG5 */ + 0xA04C04AE, /* CFG_DIG_DLL */ + 0x007FE010, /* DLL_XFORM_DQS */ + 0x00003010, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x0000000e, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + 0x20, /* Rev 2.0 */ + 300000, /* SDRAM frquency */ + 1200, /* EMC core voltage */ + 46, /* Number of EMC parameters below */ + { + 0x00000012, /* RC */ + 0x00000027, /* RFC */ + 0x0000000D, /* RAS */ + 0x00000007, /* RP */ + 0x00000007, /* R2W */ + 0x00000005, /* W2R */ + 0x00000003, /* R2P */ + 0x00000009, /* W2P */ + 0x00000006, /* RD_RCD */ + 0x00000006, /* WR_RCD */ + 0x00000003, /* RRD */ + 0x00000003, /* REXT */ + 0x00000002, /* WDV */ + 0x00000006, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x0000045f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000004, /* PDEX2WR */ + 0x00000004, /* PDEX2RD */ + 0x00000007, /* PCHG2PDEN */ + 0x00000008, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000e, /* RW2PDEN */ + 0x0000002A, /* TXSR */ + 0x00000003, /* TCKE */ + 0x0000000F, /* TFAW */ + 0x00000008, /* TRPAB */ + 0x00000005, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x000004E1, /* TREFBW */ + 0x00000005, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000282, /* FBIO_CFG5 */ + 0xE03C048B, /* CFG_DIG_DLL */ + 0x007FE010, /* DLL_XFORM_DQS */ + 0x00003010, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x0000001B, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + } +}; + // Wake Events static NvOdmWakeupPadInfo s_NvOdmWakeupPadInfo[] = @@ -649,6 +977,20 @@ static NvBool NvOdmIsE1108Hynix(void) return NvOdmIsBoardPresent(s_WhistlerE1108Hynix, NV_ARRAY_SIZE(s_WhistlerE1108Hynix)); } + +static NvBool NvOdmIsE1108Elpida(void) +{ + // A list of Whistler E1108 processor boards with Elpida LPDDR2 + // charcterized by s_NvOdmE1108ElpidaEmcConfigTable (fill in + // ID/SKU/FAB fields, revision fields are ignored) + static const NvOdmBoardInfo s_WhistlerE1108Elpida[] = + { + // ID SKU FAB Rev Minor Rev + { BOARD_ID_WHISTLER_E1108, 0x0D00, 0x03, BOARD_REV_ALL, BOARD_REV_ALL} + }; + return NvOdmIsBoardPresent(s_WhistlerE1108Elpida, + NV_ARRAY_SIZE(s_WhistlerE1108Elpida)); +} #endif static NvBool NvOdmIsCpuRailPreserved(void) @@ -1014,6 +1356,14 @@ NvOdmQuerySdramControllerConfigGet(NvU32 *pEntries, NvU32 *pRevision) *pEntries = NV_ARRAY_SIZE(s_NvOdmE1108HynixEmcConfigTable); return (const void*)s_NvOdmE1108HynixEmcConfigTable; } + else if (NvOdmIsE1108Elpida()) + { + if (pRevision) + *pRevision = s_NvOdmE1108ElpidaEmcConfigTable[0].Revision; + if (pEntries) + *pEntries = NV_ARRAY_SIZE(s_NvOdmE1108ElpidaEmcConfigTable); + return (const void*)s_NvOdmE1108ElpidaEmcConfigTable; + } #endif if (pEntries) *pEntries = 0; |