diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2010-08-04 14:05:53 +0530 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-08-05 15:55:24 -0700 |
| commit | c20ab04377ad15f9326a02000326d01a01a12df4 (patch) | |
| tree | 89ff7296670d02f248b9aa2bb79ea66b6fa883dd | |
| parent | 140b4f80dbe153d805707e07034d5c2c89538bf7 (diff) | |
[arm/tegra] Serial: Fixing tx trigger level setting.
On tegra uart, the FCR setting for different tx trigger level
is not same as the 16550 tx trigger level setting. The tegra
uart have the setting in reverse direction on tx fifo attention
level:
b00 for 16 bytes attention level.
b01 for 8 byte attention level.
b10 for 4 byte attention level
b11 for 1 byte attention level.
The rx trigger attention level match with the standard uart
FCR register setttings.
Also fixing the typo in code when setting DTR.
bug 717072
Change-Id: I3e5230de71652e3216949734f4eaca8b85e03d99
Reviewed-on: http://git-master.nvidia.com/r/4753
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
| -rwxr-xr-x | drivers/serial/tegra_hsuart.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/serial/tegra_hsuart.c b/drivers/serial/tegra_hsuart.c index 2c83447f6b89..613d2543e9a0 100755 --- a/drivers/serial/tegra_hsuart.c +++ b/drivers/serial/tegra_hsuart.c @@ -80,6 +80,13 @@ const int dma_req_sel[] = { #define TEGRA_UART_CLOCK_OFF 2 #define TEGRA_UART_SUSPEND 3 +/* Tx fifo trigger level setting in tegra uart is in + * reverse way then conventional uart */ +#define TEGRA_UART_TX_TRIG_16B 0x00 +#define TEGRA_UART_TX_TRIG_8B 0x10 +#define TEGRA_UART_TX_TRIG_4B 0x20 +#define TEGRA_UART_TX_TRIG_1B 0x30 + struct tegra_uart_port { struct uart_port uport; char port_name[32]; @@ -174,7 +181,7 @@ static void tegra_start_pio_tx(struct tegra_uart_port *t, unsigned int bytes) bytes = TEGRA_UART_FIFO_SIZE; t->fcr_shadow &= ~UART_FCR_T_TRIG_11; - t->fcr_shadow |= UART_FCR_T_TRIG_10; + t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B; uart_writeb(t, t->fcr_shadow, UART_FCR); t->tx_in_progress = TEGRA_TX_PIO; t->tx_bytes = bytes; @@ -191,7 +198,7 @@ static void tegra_start_dma_tx(struct tegra_uart_port *t, unsigned long bytes) UART_XMIT_SIZE, DMA_TO_DEVICE); t->fcr_shadow &= ~UART_FCR_T_TRIG_11; - t->fcr_shadow |= UART_FCR_T_TRIG_01; + t->fcr_shadow |= TEGRA_UART_TX_TRIG_4B; uart_writeb(t, t->fcr_shadow, UART_FCR); t->tx_bytes = bytes & ~(sizeof(u32)-1); @@ -586,7 +593,7 @@ static int tegra_uart_hw_init(struct tegra_uart_port *t) uart_writeb(t, fcr, UART_FCR); udelay(100); - uart_writeb(t, fcr, UART_FCR); + uart_writeb(t, t->fcr_shadow, UART_FCR); udelay(100); /* Set the trigger level @@ -611,7 +618,7 @@ static int tegra_uart_hw_init(struct tegra_uart_port *t) * programmed in the DMA registers. * */ t->fcr_shadow |= UART_FCR_R_TRIG_01; - t->fcr_shadow |= UART_FCR_T_TRIG_10; + t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B; uart_writeb(t, t->fcr_shadow, UART_FCR); if (t->use_rx_dma) { @@ -822,7 +829,7 @@ static void set_dtr(struct tegra_uart_port *t, bool active) if (active) mcr |= UART_MCR_DTR; else - mcr &= UART_MCR_DTR; + mcr &= ~UART_MCR_DTR; if (mcr != t->mcr_shadow) { uart_writeb(t, mcr, UART_MCR); t->mcr_shadow = mcr; |