diff options
author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2011-09-14 19:10:53 +0530 |
---|---|---|
committer | Simone Willett <swillett@nvidia.com> | 2011-09-22 17:42:50 -0700 |
commit | 337b90b5a359c4f320f58f5026fa511dca5d8031 (patch) | |
tree | 05d0d9f613fdd482348f91b76ffa213a3f494fda | |
parent | 4a3a8de8afe64c7ee497d228e5d0f1d86e9ed667 (diff) |
Arm: Tegra: Cardhu: Set slew rise/fall rates properly
Setting the slewrise and slewfall rates properly.
Bug 811303
Change-Id: I49defba97a99f9583b837ce0e95a01ded9bad35c
Reviewed-on: http://git-master/r/52367
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
-rw-r--r-- | arch/arm/mach-tegra/include/mach/pinmux.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-tegra/pinmux-t2-tables.c | 25 | ||||
-rw-r--r-- | arch/arm/mach-tegra/pinmux-t3-tables.c | 32 | ||||
-rw-r--r-- | arch/arm/mach-tegra/pinmux.c | 10 |
4 files changed, 51 insertions, 20 deletions
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index 0a1a706627ac..747e7de185f3 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -308,6 +308,10 @@ struct tegra_drive_pingroup_desc { u16 drvup_mask; u8 drvdown_offset; u16 drvdown_mask; + u8 slewrise_offset; + u16 slewrise_mask; + u8 slewfall_offset; + u16 slewfall_mask; }; struct tegra_pingroup_desc { diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-t2-tables.c index 60c5b94fb3aa..4c91f4a385cf 100644 --- a/arch/arm/mach-tegra/pinmux-t2-tables.c +++ b/arch/arm/mach-tegra/pinmux-t2-tables.c @@ -32,14 +32,19 @@ #include <mach/suspend.h> #include "gpio-names.h" -#define SET_DRIVE_PINGROUP(pg_name, r, drv_down_offset, drv_down_mask, drv_up_offset, drv_up_mask) \ - [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ - .name = #pg_name, \ - .reg = r, \ - .drvup_offset = drv_up_offset, \ - .drvup_mask = drv_up_mask, \ - .drvdown_offset = drv_down_offset, \ - .drvdown_mask = drv_down_mask, \ +#define SET_DRIVE_PINGROUP(pg_name, r, drv_down_offset, drv_down_mask, drv_up_offset, drv_up_mask, \ + slew_rise_offset, slew_rise_mask, slew_fall_offset, slew_fall_mask) \ + [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ + .name = #pg_name, \ + .reg = r, \ + .drvup_offset = drv_up_offset, \ + .drvup_mask = drv_up_mask, \ + .drvdown_offset = drv_down_offset, \ + .drvdown_mask = drv_down_mask, \ + .slewrise_offset = slew_rise_offset, \ + .slewrise_mask = slew_rise_mask, \ + .slewfall_offset = slew_fall_offset, \ + .slewfall_mask = slew_fall_mask, \ } #define DEFAULT_DRIVE_PINGROUP(pg_name, r) \ @@ -50,6 +55,10 @@ .drvup_mask = 0x1f, \ .drvdown_offset = 12, \ .drvdown_mask = 0x1f, \ + .slewrise_offset = 28, \ + .slewrise_mask = 0x3, \ + .slewfall_offset = 30, \ + .slewfall_mask = 0x3, \ } const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { diff --git a/arch/arm/mach-tegra/pinmux-t3-tables.c b/arch/arm/mach-tegra/pinmux-t3-tables.c index d14afa733b96..d1b3f1134a92 100644 --- a/arch/arm/mach-tegra/pinmux-t3-tables.c +++ b/arch/arm/mach-tegra/pinmux-t3-tables.c @@ -32,7 +32,8 @@ #include <mach/suspend.h> #include "gpio-names.h" -#define SET_DRIVE_PINGROUP(pg_name, r, drv_down_offset, drv_down_mask, drv_up_offset, drv_up_mask) \ +#define SET_DRIVE_PINGROUP(pg_name, r, drv_down_offset, drv_down_mask, drv_up_offset, drv_up_mask, \ + slew_rise_offset, slew_rise_mask, slew_fall_offset, slew_fall_mask) \ [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ .name = #pg_name, \ .reg = r, \ @@ -40,6 +41,10 @@ .drvup_mask = drv_up_mask, \ .drvdown_offset = drv_down_offset, \ .drvdown_mask = drv_down_mask, \ + .slewrise_offset = slew_rise_offset, \ + .slewrise_mask = slew_rise_mask, \ + .slewfall_offset = slew_fall_offset, \ + .slewfall_mask = slew_fall_mask, \ } #define DEFAULT_DRIVE_PINGROUP(pg_name, r) \ @@ -50,6 +55,10 @@ .drvup_mask = 0x1f, \ .drvdown_offset = 12, \ .drvdown_mask = 0x1f, \ + .slewrise_offset = 28, \ + .slewrise_mask = 0x3, \ + .slewfall_offset = 30, \ + .slewfall_mask = 0x3, \ } const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { @@ -70,21 +79,28 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE DEFAULT_DRIVE_PINGROUP(DBG, 0x8a0), DEFAULT_DRIVE_PINGROUP(LCD1, 0x8a4), DEFAULT_DRIVE_PINGROUP(LCD2, 0x8a8), - SET_DRIVE_PINGROUP(SDIO2, 0x8ac, 12, 0x7f, 20, 0x7f), - SET_DRIVE_PINGROUP(SDIO3, 0x8b0, 12, 0x7f, 20, 0x7f), + SET_DRIVE_PINGROUP(SDIO2, 0x8ac, 12, 0x7f, 20, 0x7f, + 28, 0x3, 30, 0x3), + SET_DRIVE_PINGROUP(SDIO3, 0x8b0, 12, 0x7f, 20, 0x7f, + 28, 0x3, 30, 0x3), DEFAULT_DRIVE_PINGROUP(SPI, 0x8b4), DEFAULT_DRIVE_PINGROUP(UAA, 0x8b8), DEFAULT_DRIVE_PINGROUP(UAB, 0x8bc), DEFAULT_DRIVE_PINGROUP(UART2, 0x8c0), DEFAULT_DRIVE_PINGROUP(UART3, 0x8c4), DEFAULT_DRIVE_PINGROUP(VI1, 0x8c8), - SET_DRIVE_PINGROUP(SDIO1, 0x8ec, 12, 0x7f, 20, 0x7f), + SET_DRIVE_PINGROUP(SDIO1, 0x8ec, 12, 0x7f, 20, 0x7f, + 28, 0x3, 30, 0x3), DEFAULT_DRIVE_PINGROUP(CRT, 0x8f8), DEFAULT_DRIVE_PINGROUP(DDC, 0x8fc), - SET_DRIVE_PINGROUP(GMA, 0x900, 14, 0x1f, 19, 0x1f), - SET_DRIVE_PINGROUP(GMB, 0x904, 14, 0x1f, 19, 0x1f), - SET_DRIVE_PINGROUP(GMC, 0x908, 14, 0x1f, 19, 0x1f), - SET_DRIVE_PINGROUP(GMD, 0x90c, 14, 0x1f, 19, 0x1f), + SET_DRIVE_PINGROUP(GMA, 0x900, 14, 0x1f, 19, 0x1f, + 24, 0xf, 28, 0xf), + SET_DRIVE_PINGROUP(GMB, 0x904, 14, 0x1f, 19, 0x1f, + 24, 0xf, 28, 0xf), + SET_DRIVE_PINGROUP(GMC, 0x908, 14, 0x1f, 19, 0x1f, + 24, 0xf, 28, 0xf), + SET_DRIVE_PINGROUP(GMD, 0x90c, 14, 0x1f, 19, 0x1f, + 24, 0xf, 28, 0xf), DEFAULT_DRIVE_PINGROUP(GME, 0x910), DEFAULT_DRIVE_PINGROUP(GMF, 0x914), DEFAULT_DRIVE_PINGROUP(GMG, 0x918), diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index 60eb1788b3bf..d2bd46b62ed0 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c @@ -773,8 +773,9 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg, spin_lock_irqsave(&mux_lock, flags); reg = pg_readl(drive_pingroups[pg].reg); - reg &= ~(0x3 << 28); - reg |= slew_rising << 28; + reg &= ~(drive_pingroups[pg].slewrise_mask << + drive_pingroups[pg].slewrise_offset); + reg |= slew_rising << drive_pingroups[pg].slewrise_offset; pg_writel(reg, drive_pingroups[pg].reg); spin_unlock_irqrestore(&mux_lock, flags); @@ -796,8 +797,9 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg, spin_lock_irqsave(&mux_lock, flags); reg = pg_readl(drive_pingroups[pg].reg); - reg &= ~(0x3 << 30); - reg |= slew_falling << 30; + reg &= ~(drive_pingroups[pg].slewfall_mask << + drive_pingroups[pg].slewfall_offset); + reg |= slew_falling << drive_pingroups[pg].slewfall_offset; pg_writel(reg, drive_pingroups[pg].reg); spin_unlock_irqrestore(&mux_lock, flags); |