ARM: tegra: dvfs: Update Tegra3 EMC DFS

Updated Tegra3 EMC clock change procedure with periodic qrst support,
and EMC DFS tables.

Bug 836260

Change-Id: Ia3d7f58bf61ee6e695ab62f934388d4c1b4d2079
Reviewed-on: http://git-master/r/35321
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>

3 files changed, 393 insertions, 144 deletions

diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c
index 52737aa80d48..f30a5bd5869d 100644
--- a/arch/arm/mach-tegra/board-cardhu-memory.c
+++ b/arch/arm/mach-tegra/board-cardhu-memory.c
@@ -138,6 +138,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
 		},
 		0x00000040,	/* EMC_ZCAL_WAIT_CNT after clock change */
 		0x001fffff,	/* EMC_AUTO_CAL_INTERVAL */
+		0x00000000,	/* EMC_CFG.PERIODIC_QRST */
 		0x00001221,	/* Mode Register 0 */
 		0x00100003,	/* Mode Register 1 */
 		0x00200008,	/* Mode Register 2 */
@@ -254,6 +255,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
 		},
 		0x00000040,	/* EMC_ZCAL_WAIT_CNT after clock change */
 		0x001fffff,	/* EMC_AUTO_CAL_INTERVAL */
+		0x00000000,	/* EMC_CFG.PERIODIC_QRST */
 		0x00001221,	/* Mode Register 0 */
 		0x00100003,	/* Mode Register 1 */
 		0x00200008,	/* Mode Register 2 */
@@ -370,6 +372,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
 		},
 		0x00000040,	/* EMC_ZCAL_WAIT_CNT after clock change */
 		0x001fffff,	/* EMC_AUTO_CAL_INTERVAL */
+		0x00000000,	/* EMC_CFG.PERIODIC_QRST */
 		0x00001221,	/* Mode Register 0 */
 		0x00100003,	/* Mode Register 1 */
 		0x00200008,	/* Mode Register 2 */
@@ -486,6 +489,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
 		},
 		0x00000040,	/* EMC_ZCAL_WAIT_CNT after clock change */
 		0x00000010,	/* EMC_AUTO_CAL_INTERVAL */
+		0x00000000,	/* EMC_CFG.PERIODIC_QRST */
 		0x00001941,	/* Mode Register 0 */
 		0x00100002,	/* Mode Register 1 */
 		0x00200008,	/* Mode Register 2 */
@@ -602,6 +606,7 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
 		},
 		0x00000040,	/* EMC_ZCAL_WAIT_CNT after clock change */
 		0x00000010,	/* EMC_AUTO_CAL_INTERVAL */
+		0x00000000,	/* EMC_CFG.PERIODIC_QRST */
 		0x00001941,	/* Mode Register 0 */
 		0x00100002,	/* Mode Register 1 */
 		0x00200008,	/* Mode Register 2 */
@@ -610,67 +615,67 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
 
 static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 	{
-		0x30,		/* Rev 3.0 */
-		400000,		/* SDRAM frequency */
+		0x30,       /* Rev 3.0 */
+		27000,      /* SDRAM frequency */
 		{
-			0x00000012, /* EMC_RC */
-			0x0000003e, /* EMC_RFC */
-			0x0000000c, /* EMC_RAS */
-			0x00000004, /* EMC_RP */
+			0x00000001, /* EMC_RC */
+			0x00000004, /* EMC_RFC */
+			0x00000000, /* EMC_RAS */
+			0x00000000, /* EMC_RP */
 			0x00000002, /* EMC_R2W */
-			0x00000008, /* EMC_W2R */
-			0x00000002, /* EMC_R2P */
-			0x0000000a, /* EMC_W2P */
-			0x00000004, /* EMC_RD_RCD */
-			0x00000004, /* EMC_WR_RCD */
-			0x00000002, /* EMC_RRD */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000000, /* EMC_RD_RCD */
+			0x00000000, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
 			0x00000001, /* EMC_REXT */
 			0x00000000, /* EMC_WEXT */
-			0x00000004, /* EMC_WDV */
-			0x00000006, /* EMC_QUSE */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_QUSE */
 			0x00000004, /* EMC_QRST */
-			0x0000000b, /* EMC_QSAFE */
+			0x00000007, /* EMC_QSAFE */
 			0x0000000c, /* EMC_RDV */
-			0x00000bf0, /* EMC_REFRESH */
+			0x000000cb, /* EMC_REFRESH */
 			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000002fc, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000008, /* EMC_PDEX2WR */
-			0x00000008, /* EMC_PDEX2RD */
+			0x00000032, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
 			0x00000001, /* EMC_PCHG2PDEN */
 			0x00000000, /* EMC_ACT2PDEN */
-			0x00000008, /* EMC_AR2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
 			0x0000000f, /* EMC_RW2PDEN */
-			0x00000044, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x0000000a, /* EMC_TCKE */
-			0x0000000c, /* EMC_TFAW */
+			0x00000005, /* EMC_TXSR */
+			0x00000005, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000001, /* EMC_TFAW */
 			0x00000000, /* EMC_TRPAB */
 			0x00000004, /* EMC_TCLKSTABLE */
 			0x00000005, /* EMC_TCLKSTOP */
-			0x00000c30, /* EMC_TREFBW */
+			0x000000d3, /* EMC_TREFBW */
 			0x00000000, /* EMC_QUSE_EXTRA */
 			0x00000004, /* EMC_FBIO_CFG6 */
 			0x00000000, /* EMC_ODT_WRITE */
 			0x00000000, /* EMC_ODT_READ */
-			0x00007088, /* EMC_FBIO_CFG5 */
-			0x001d0084, /* EMC_CFG_DIG_DLL */
+			0x00006288, /* EMC_FBIO_CFG5 */
+			0x007800a4, /* EMC_CFG_DIG_DLL */
 			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00030000, /* EMC_DLL_XFORM_DQS0 */
-			0x00030000, /* EMC_DLL_XFORM_DQS1 */
-			0x00030000, /* EMC_DLL_XFORM_DQS2 */
-			0x00030000, /* EMC_DLL_XFORM_DQS3 */
-			0x00000010, /* EMC_DLL_XFORM_DQS4 */
-			0x00000010, /* EMC_DLL_XFORM_DQS5 */
-			0x00000010, /* EMC_DLL_XFORM_DQS6 */
-			0x00000010, /* EMC_DLL_XFORM_DQS7 */
+			0x00080000, /* EMC_DLL_XFORM_DQS0 */
+			0x00080000, /* EMC_DLL_XFORM_DQS1 */
+			0x00080000, /* EMC_DLL_XFORM_DQS2 */
+			0x00080000, /* EMC_DLL_XFORM_DQS3 */
+			0x00080000, /* EMC_DLL_XFORM_DQS4 */
+			0x00080000, /* EMC_DLL_XFORM_DQS5 */
+			0x00080000, /* EMC_DLL_XFORM_DQS6 */
+			0x00080000, /* EMC_DLL_XFORM_DQS7 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-			0x00000018, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000018, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000018, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000018, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
@@ -679,97 +684,332 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
+			0x00080000, /* EMC_DLL_XFORM_DQ0 */
+			0x00080000, /* EMC_DLL_XFORM_DQ1 */
+			0x00080000, /* EMC_DLL_XFORM_DQ2 */
+			0x00080000, /* EMC_DLL_XFORM_DQ3 */
 			0x000002a0, /* EMC_XM2CMDPADCTRL */
-			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
 			0x00000000, /* EMC_XM2DQPADCTRL2 */
 			0x77ffc084, /* EMC_XM2CLKPADCTRL */
-			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x01f1f108, /* EMC_XM2COMPPADCTRL */
 			0x03037404, /* EMC_XM2VTTGENPADCTRL */
 			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
-			0x080001e8, /* EMC_XM2QUSEPADCTRL */
-			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000000, /* EMC_XM2DQSPADCTRL3 */
 			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x01c0000c, /* EMC_MRS_WAIT_CNT */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
 			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
-			0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000006, /* MC_EMEM_ARB_CFG */
-			0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x8000076e, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x80000014, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000009, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
 			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
 			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
 			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030202, /* MC_EMEM_ARB_DA_TURNS */
-			0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
-			0x7566120a, /* MC_EMEM_ARB_MISC0 */
+			0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
+			0x72830504, /* MC_EMEM_ARB_MISC0 */
 			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
 		},
-		0x00000040,	/* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff,	/* EMC_AUTO_CAL_INTERVAL */
-		0x80000521,	/* Mode Register 0 */
-		0x80100002,	/* Mode Register 1 */
-		0x80200000,	/* Mode Register 2 */
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
 	},
 	{
-		0x30,		/* Rev 3.0 */
-		800000,		/* SDRAM frequency */
+		0x30,       /* Rev 3.0 */
+		54000,      /* SDRAM frequency */
 		{
-			0x00000025, /* EMC_RC */
-			0x0000007e, /* EMC_RFC */
-			0x0000001a, /* EMC_RAS */
-			0x00000009, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000d, /* EMC_W2R */
-			0x00000004, /* EMC_R2P */
-			0x00000013, /* EMC_W2P */
-			0x00000009, /* EMC_RD_RCD */
-			0x00000009, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RC */
+			0x00000008, /* EMC_RFC */
+			0x00000001, /* EMC_RAS */
+			0x00000000, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000000, /* EMC_RD_RCD */
+			0x00000000, /* EMC_WR_RCD */
 			0x00000003, /* EMC_RRD */
 			0x00000001, /* EMC_REXT */
 			0x00000000, /* EMC_WEXT */
-			0x00000007, /* EMC_WDV */
-			0x0000000b, /* EMC_QUSE */
-			0x00000009, /* EMC_QRST */
-			0x0000000b, /* EMC_QSAFE */
-			0x00000011, /* EMC_RDV */
-			0x00001820, /* EMC_REFRESH */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x00000007, /* EMC_QSAFE */
+			0x0000000c, /* EMC_RDV */
+			0x00000198, /* EMC_REFRESH */
 			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000012, /* EMC_PDEX2WR */
-			0x00000012, /* EMC_PDEX2RD */
+			0x00000066, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
 			0x00000001, /* EMC_PCHG2PDEN */
 			0x00000000, /* EMC_ACT2PDEN */
-			0x0000000f, /* EMC_AR2PDEN */
-			0x00000018, /* EMC_RW2PDEN */
-			0x00000088, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000014, /* EMC_TCKE */
-			0x00000018, /* EMC_TFAW */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x0000000a, /* EMC_TXSR */
+			0x0000000a, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000002, /* EMC_TFAW */
 			0x00000000, /* EMC_TRPAB */
-			0x00000007, /* EMC_TCLKSTABLE */
-			0x00000008, /* EMC_TCLKSTOP */
-			0x00001860, /* EMC_TREFBW */
-			0x0000000c, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x000001a6, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
 			0x00000004, /* EMC_FBIO_CFG6 */
 			0x00000000, /* EMC_ODT_WRITE */
 			0x00000000, /* EMC_ODT_READ */
-			0x00005088, /* EMC_FBIO_CFG5 */
-			0x00070084, /* EMC_CFG_DIG_DLL */
+			0x00006288, /* EMC_FBIO_CFG5 */
+			0x007800a4, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00080000, /* EMC_DLL_XFORM_DQS0 */
+			0x00080000, /* EMC_DLL_XFORM_DQS1 */
+			0x00080000, /* EMC_DLL_XFORM_DQS2 */
+			0x00080000, /* EMC_DLL_XFORM_DQS3 */
+			0x00080000, /* EMC_DLL_XFORM_DQS4 */
+			0x00080000, /* EMC_DLL_XFORM_DQS5 */
+			0x00080000, /* EMC_DLL_XFORM_DQS6 */
+			0x00080000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00080000, /* EMC_DLL_XFORM_DQ0 */
+			0x00080000, /* EMC_DLL_XFORM_DQ1 */
+			0x00080000, /* EMC_DLL_XFORM_DQ2 */
+			0x00080000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
+			0x01f1f108, /* EMC_XM2COMPPADCTRL */
+			0x03037404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000000, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000076e, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x80000014, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
+			0x72830504, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+	},
+	{
+		0x30,       /* Rev 3.0 */
+		108000,     /* SDRAM frequency */
+		{
+			0x00000005, /* EMC_RC */
+			0x00000011, /* EMC_RFC */
+			0x00000003, /* EMC_RAS */
+			0x00000001, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000001, /* EMC_RD_RCD */
+			0x00000001, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x00000007, /* EMC_QSAFE */
+			0x0000000c, /* EMC_RDV */
+			0x00000330, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000000cc, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000013, /* EMC_TXSR */
+			0x00000013, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x0000034b, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00006288, /* EMC_FBIO_CFG5 */
+			0x007800a4, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00080000, /* EMC_DLL_XFORM_DQS0 */
+			0x00080000, /* EMC_DLL_XFORM_DQS1 */
+			0x00080000, /* EMC_DLL_XFORM_DQS2 */
+			0x00080000, /* EMC_DLL_XFORM_DQS3 */
+			0x00080000, /* EMC_DLL_XFORM_DQS4 */
+			0x00080000, /* EMC_DLL_XFORM_DQS5 */
+			0x00080000, /* EMC_DLL_XFORM_DQS6 */
+			0x00080000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00080000, /* EMC_DLL_XFORM_DQ0 */
+			0x00080000, /* EMC_DLL_XFORM_DQ1 */
+			0x00080000, /* EMC_DLL_XFORM_DQ2 */
+			0x00080000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
+			0x01f1f108, /* EMC_XM2COMPPADCTRL */
+			0x03037404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000000, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000076e, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000001, /* MC_EMEM_ARB_CFG */
+			0x80000014, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
+			0x72830504, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+	},
+	{
+		0x30,       /* Rev 3.0 */
+		533000,     /* SDRAM frequency */
+		{
+			0x00000018, /* EMC_RC */
+			0x00000054, /* EMC_RFC */
+			0x00000011, /* EMC_RAS */
+			0x00000006, /* EMC_RP */
+			0x00000003, /* EMC_R2W */
+			0x00000009, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x0000000d, /* EMC_W2P */
+			0x00000006, /* EMC_RD_RCD */
+			0x00000006, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000008, /* EMC_QUSE */
+			0x00000006, /* EMC_QRST */
+			0x00000008, /* EMC_QSAFE */
+			0x00000010, /* EMC_RDV */
+			0x00000ffd, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000003ff, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000000a, /* EMC_AR2PDEN */
+			0x00000012, /* EMC_RW2PDEN */
+			0x0000005b, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000010, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000005, /* EMC_TCLKSTABLE */
+			0x00000006, /* EMC_TCLKSTOP */
+			0x0000103e, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00007088, /* EMC_FBIO_CFG5 */
+			0xf0120441, /* EMC_CFG_DIG_DLL */
 			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
 			0x00010000, /* EMC_DLL_XFORM_DQS0 */
 			0x00010000, /* EMC_DLL_XFORM_DQS1 */
@@ -779,14 +1019,14 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00010000, /* EMC_DLL_XFORM_DQS5 */
 			0x00010000, /* EMC_DLL_XFORM_DQS6 */
 			0x00010000, /* EMC_DLL_XFORM_DQS7 */
-			0x00010000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00010000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00010000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00010000, /* EMC_DLL_XFORM_QUSE3 */
-			0x00010000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00010000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00010000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00010000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
@@ -795,51 +1035,52 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x00018000, /* EMC_DLL_XFORM_DQ0 */
-			0x00018000, /* EMC_DLL_XFORM_DQ1 */
-			0x00018000, /* EMC_DLL_XFORM_DQ2 */
-			0x00018000, /* EMC_DLL_XFORM_DQ3 */
-			0x000002a0, /* EMC_XM2CMDPADCTRL */
-			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00020000, /* EMC_DLL_XFORM_DQ0 */
+			0x00020000, /* EMC_DLL_XFORM_DQ1 */
+			0x00020000, /* EMC_DLL_XFORM_DQ2 */
+			0x00020000, /* EMC_DLL_XFORM_DQ3 */
+			0x000006a0, /* EMC_XM2CMDPADCTRL */
+			0x0800013d, /* EMC_XM2DQSPADCTRL2 */
 			0x00000000, /* EMC_XM2DQPADCTRL2 */
 			0x77ffc084, /* EMC_XM2CLKPADCTRL */
-			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x01f1f50f, /* EMC_XM2COMPPADCTRL */
 			0x07077404, /* EMC_XM2VTTGENPADCTRL */
-			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
-			0x080001e8, /* EMC_XM2QUSEPADCTRL */
-			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x0800011d, /* EMC_XM2QUSEPADCTRL */
+			0x08000021, /* EMC_XM2DQSPADCTRL3 */
 			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x0180000c, /* EMC_MRS_WAIT_CNT */
-			0xa0f11e1e, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x01ab000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10404, /* EMC_AUTO_CAL_CONFIG */
 			0x00000000, /* EMC_CTT */
 			0x00000000, /* EMC_CTT_DURATION */
-			0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
-			0x0000000c, /* MC_EMEM_ARB_CFG */
-			0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
-			0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
-			0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x000020ae, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000008, /* MC_EMEM_ARB_CFG */
+			0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+			0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000008, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
 			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
 			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
-			0x08040202, /* MC_EMEM_ARB_DA_TURNS */
-			0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
-			0x72ac2414, /* MC_EMEM_ARB_MISC0 */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+			0x0010090d, /* MC_EMEM_ARB_DA_COVERS */
+			0x7028180e, /* MC_EMEM_ARB_MISC0 */
 			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
 		},
-		0x00000040,	/* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff,	/* EMC_AUTO_CAL_INTERVAL */
-		0x80000d71,	/* Mode Register 0 */
-		0x80100002,	/* Mode Register 1 */
-		0x80200018,	/* Mode Register 2 */
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x00000010, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80001941, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
 	},
 };
 
diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c
index d4ee7d9f3af2..cdf1fc2b0279 100644
--- a/arch/arm/mach-tegra/tegra3_emc.c
+++ b/arch/arm/mach-tegra/tegra3_emc.c
@@ -521,8 +521,13 @@ static noinline void emc_set_clock(const struct tegra_emc_table *next_timing,
 		emc_writel(DRAM_BROADCAST(dram_dev_num), EMC_SELF_REF);
 
 	/* 10. restore periodic QRST */
-	if (qrst_used)
+	if ((qrst_used) || (next_timing->emc_periodic_qrst !=
+			    last_timing->emc_periodic_qrst)) {
+		emc_cfg_reg = next_timing->emc_periodic_qrst ?
+			emc_cfg_reg | EMC_CFG_PERIODIC_QRST :
+			emc_cfg_reg & (~EMC_CFG_PERIODIC_QRST);
 		periodic_qrst_restore(emc_cfg_reg, emc_dbg_reg);
+	}
 
 	/* 11. set dram mode registers */
 	set_dram_mode(next_timing, last_timing, dll_change);
@@ -576,6 +581,8 @@ static inline void emc_get_timing(struct tegra_emc_table *timing)
 	timing->emc_mode_reset = 0;
 	timing->emc_mode_1 = 0;
 	timing->emc_mode_2 = 0;
+	timing->emc_periodic_qrst = (emc_readl(EMC_CFG) &
+				     EMC_CFG_PERIODIC_QRST) ? 1 : 0;
 }
 
 /* The EMC registers have shadow registers. When the EMC clock is updated
diff --git a/arch/arm/mach-tegra/tegra3_emc.h b/arch/arm/mach-tegra/tegra3_emc.h
index e4d40dd500e6..bb4cad6e96a7 100644
--- a/arch/arm/mach-tegra/tegra3_emc.h
+++ b/arch/arm/mach-tegra/tegra3_emc.h
@@ -34,6 +34,7 @@ struct tegra_emc_table {
 	/* updated separately under some conditions */
 	u32 emc_zcal_cnt_long;
 	u32 emc_acal_interval;
+	u32 emc_periodic_qrst;
 	u32 emc_mode_reset;
 	u32 emc_mode_1;
 	u32 emc_mode_2;