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authorMugunthan V N <mugunthanvnm@ti.com>2014-04-10 14:23:24 +0530
committerDavid S. Miller <davem@davemloft.net>2014-04-11 16:27:41 -0400
commitf63a975e8f07a75dbf0386402788330d0bebd8d8 (patch)
tree03aa9f5740a33f39d7ccd643048e63e94097b73b
parent16e5c57da61cda26998bee91a327960ebd1562f6 (diff)
drivers: net: cpsw: enable interrupts after napi enable and clearing previous interrupts
When the Ethernet interface is put down and up with heavy Ethernet traffic, then there is prossibility of an interrupt waiting in irq controller to be processed, so when the interface is brought up again just after enable interrupt, it goes to ISR due to the previous unhandled interrutp and in ISR napi is not scheduled as the napi is not enabled in ndo_open which results in disabled interrupt for CPSW and no packets are received in cpsw. So this patch moves enabling of interupts after napi_enable and clearing CPDMA interrupts. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/ti/cpsw.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 4e3d197ce55a..36aa109416c4 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1252,6 +1252,12 @@ static int cpsw_ndo_open(struct net_device *ndev)
cpsw_set_coalesce(ndev, &coal);
}
+ napi_enable(&priv->napi);
+ cpdma_ctlr_start(priv->dma);
+ cpsw_intr_enable(priv);
+ cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
+ cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
+
prim_cpsw = cpsw_get_slave_priv(priv, 0);
if (prim_cpsw->irq_enabled == false) {
if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
@@ -1260,12 +1266,6 @@ static int cpsw_ndo_open(struct net_device *ndev)
}
}
- napi_enable(&priv->napi);
- cpdma_ctlr_start(priv->dma);
- cpsw_intr_enable(priv);
- cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
- cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
-
if (priv->data.dual_emac)
priv->slaves[priv->emac_port].open_stat = true;
return 0;