tegra RM: Separated DDR2 and LPDDR2 EMC DFS parameters.

Separated EMC DFS parameters for DDR2 and LPDDR2 so they can be tuned
independently. Kept all parameters for both SDRAM types unchanged with the
exception of LPDDR2 EMC activity margin - set at 100% (2x); this change is
a partial revert of commit I8467a52d that caused perf regression on LPDDR2
platforms (no perf regression is observed for DDR2).

Change-Id: I193732a376e0a477aef3faf2348b4187d8aca40f
Reviewed-on: http://git-master/r/1165
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

3 files changed, 41 insertions, 21 deletions

diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
index ae73a896a722..a5ddb03870db 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
@@ -60,28 +60,27 @@
 // EMC MODULE INTERFACES
 /*****************************************************************************/
 
-void NvRmPrivAp20EmcMinFreqSet(NvRmDfs* pDfs)
+void NvRmPrivAp20EmcParametersAdjust(NvRmDfs* pDfs)
 {
-    NvRmFreqKHz f;
+    NvRmDfsParam EmcParamDddr2 = { NVRM_DFS_PARAM_EMC_AP20_DDR2 };
+    NvRmDfsParam EmcParamLpDddr2 = { NVRM_DFS_PARAM_EMC_AP20_LPDDR2 };
+
     NvU32 RegValue = NV_REGR(pDfs->hRm,
         NvRmPrivModuleID_ExternalMemoryController, 0, EMC_FBIO_CFG5_0);
 
     switch (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_TYPE, RegValue))
     {
         case EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2:
-            f = NVRM_AP20_LPDDR2_MIN_KHZ;
+            pDfs->DfsParameters[NvRmDfsClockId_Emc] = EmcParamLpDddr2;
             break;
 
         case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2:
-            f = NVRM_AP20_DDR2_MIN_KHZ;
+            pDfs->DfsParameters[NvRmDfsClockId_Emc] = EmcParamDddr2;
             break;
 
         default:
-            f = 0;
             NV_ASSERT(!"Not supported DRAM type");
     }
-    pDfs->DfsParameters[NvRmDfsClockId_Emc].MinKHz =
-        NV_MAX(pDfs->DfsParameters[NvRmDfsClockId_Emc].MinKHz, f);
 }
 
 NvError NvRmPrivAp20EmcMonitorsInit(NvRmDfs* pDfs)
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
index 2e1092c02f57..9d5b7431d57a 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
@@ -188,9 +188,14 @@ extern "C"
 /**
  * Default DFS algorithm parameters for EMC clock domain
  */
-#define NVRM_DFS_PARAM_EMC_AP20 \
+
+// Defines minimum scaling limit for each supported SDRAM type
+#define NVRM_AP20_DDR2_MIN_KHZ (50000)
+#define NVRM_AP20_LPDDR2_MIN_KHZ (18000)
+
+#define NVRM_DFS_PARAM_EMC_AP20_DDR2 \
     NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
-    18000,  /* Minimum domain frequency 18 MHz (for all SDRAM types) */ \
+    NVRM_AP20_DDR2_MIN_KHZ,  /* Minimum domain frequency for DDR2 */ \
     1000,   /* Frequency change upper band 1 MHz */ \
     1000,   /* Frequency change lower band 1 MHz */ \
     {          /* RT starvation control parameters */ \
@@ -205,11 +210,28 @@ extern "C"
     },\
     1,      /* Relative adjustement of average freqiency 1/2^1 ~ 50% */ \
     0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
-    1       /* NRT idle cycles threshold = 1 */ 
+    1       /* NRT idle cycles threshold = 1 */
 
-// Defines minimum scaling limit for each supported SDRAM type
-#define NVRM_AP20_DDR2_MIN_KHZ (50000)
-#define NVRM_AP20_LPDDR2_MIN_KHZ (18000)
+#define NVRM_DFS_PARAM_EMC_AP20_LPDDR2 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    NVRM_AP20_LPDDR2_MIN_KHZ,  /* Minimum domain frequency for LPDDR2 */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        16000, /* Fixed frequency RT boost increase 16 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    0,      /* Relative adjustement of average freqiency 1/2^0 ~ 100% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */
+
+#define NVRM_DFS_PARAM_EMC_AP20 NVRM_DFS_PARAM_EMC_AP20_LPDDR2
 
 /**
  * Defines CPU frequency threshold for slave CPU1 power management:
@@ -236,12 +258,12 @@ extern "C"
 /*****************************************************************************/
 
 /**
- * Set minimum EMC frequency based on the SDRAM type selected by current EMC
- * configuration.
+ * Adjust EMC scaling algorithm parameters based on the SDRAM type selected by
+ * current EMC configuration.
  *
  * @param pDfs - A pointer to DFS structure.
  */
-void NvRmPrivAp20EmcMinFreqSet(NvRmDfs* pDfs);
+void NvRmPrivAp20EmcParametersAdjust(NvRmDfs* pDfs);
 
 /**
  * Initializes activity monitors within the DFS module. Only activity
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
index 37ddba022dc4..425ad8dcf4e0 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
@@ -732,6 +732,10 @@ static void DfsParametersInit(NvRmDfs* pDfs)
 
     #undef INIT_PARAM
 
+    // Adjust EMC parameters as required for particular SDRAM type
+    if (pDfs->hRm->ChipId.Id == 0x20)
+        NvRmPrivAp20EmcParametersAdjust(pDfs);
+
     // Update minimum frequency boundary for DFS clocks as required for
     // download transport support
     switch (NvRmPrivGetDownloadTransport(pDfs->hRm))
@@ -766,11 +770,6 @@ static void DfsParametersInit(NvRmDfs* pDfs)
             break;
     }
 
-    // Adjust minimum frequency boundary for EMC as required for
-    // particular SDRAM type
-    if (pDfs->hRm->ChipId.Id == 0x20)
-        NvRmPrivAp20EmcMinFreqSet(pDfs);
-
     // CPU clock H/w limits
     pClimits = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu);
     HwLimitsKHz[NvRmDfsClockId_Cpu] = *pClimits;