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authortkasivajhula <tkasivajhula@nvidia.com>2010-05-18 18:47:12 -0700
committerGary King <gking@nvidia.com>2010-05-18 21:17:28 -0700
commit0dcf0d73e281c4b281d35d43c8a4844f1465d313 (patch)
treea76a0489e67a4df9136bdf53a8fff282cdc5bedb
parent187d29263033449288573b6243d65f0fd5aef149 (diff)
tegra power: Don't power gate the TD partition.
Occasionally, ungating the TD partition when exiting LP0 causes the entire system to crash. This WAR avoids this issue by keeping the TD partition always on. Change-Id: I20e09b3014feb011f922e654e2fb6d28a956d693 Reviewed-on: http://git-master/r/1435 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
index d9fd9f3d1251..7353cee96be4 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
@@ -73,6 +73,7 @@
// TODO: check MPE voltage control calls before enabling
#define NV_POWER_GATE_MPE (0)
+#define NV_TD_PWRGATE_WORKAROUND_688639 1
// Power Group -to- Power Gating Ids mapping
static const NvU32* s_PowerGroupIds = NULL;
static NvBool s_UngateOnResume[NV_POWERGROUP_MAX] = {0};
@@ -225,6 +226,14 @@ PowerGroupPowerControl(
if (Enable == (Status != 0x0))
return;
+#if NV_TD_PWRGATE_WORKAROUND_688639
+ //Don't turn off the TD partition.
+ //Turning it on is ok.
+ if (PowerGroup == NV_POWERGROUP_TD && !Enable)
+ {
+ return;
+ }
+#endif
/*
* Gating procedure:
* - assert resets to all modules in power group