diff options
author | John Kramer <john.kramer@motorola.com> | 2011-02-04 11:32:19 -0600 |
---|---|---|
committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-07-12 15:04:42 -0700 |
commit | 6d4f3efddb05a5538f90a4b7e23bbb8a493a9dfa (patch) | |
tree | 2c4a25adb0e13c83d7503bbf09468e1c06394c08 | |
parent | 358a8f04e7adc6b95cca9ef131489525822e7a01 (diff) |
media: video: tegra: Correct mclk settings for ov5650
Signed-off-by: John Kramer <john.kramer@motorola.com>
(cherry picked from commit 498e62c0b48548b07481927e02decd9a00c815d2)
Change-Id: Ib616ea4b9ca2a8915db59c60c84511b2b0ac725f
Reviewed-on: http://git-master/r/36701
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Tested-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
-rw-r--r-- | drivers/media/video/tegra/ov5650.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/media/video/tegra/ov5650.c b/drivers/media/video/tegra/ov5650.c index 80b87bc23c50..c4b3e7275d8c 100644 --- a/drivers/media/video/tegra/ov5650.c +++ b/drivers/media/video/tegra/ov5650.c @@ -308,7 +308,7 @@ static struct ov5650_reg mode_2080x1164[] = { {0x300f, 0x8f}, // PLL control00 R_SELD5 [7:6] div by 4 R_DIVL [2] two lane div 1 SELD2P5 [1:0] div 2.5 pg 99 {0x3010, 0x10}, // PLL control01 DIVM [3:0] DIVS [7:4] div 1 pg 99 - {0x3011, 0x14}, // PLL control02 R_DIVP [5:0] div 20 pg 99 + {0x3011, 0x18}, // PLL control02 R_DIVP [5:0] div 24 pg 99 (20Mhz Mclk) {0x3012, 0x02}, // PLL CTR 03, default {0x3503, 0x33}, // AEC auto AGC auto gain has delay of 2 frames. pg 38 |