tegra: Tristating the unsed pin groups in VDDIO_NAND rail.

The power numbers were high on the VDDIO_NAND rail, when the Nand module
was not present in EMMC boot. Doing a Pullup of the unused pin groups
and tristating the pad groups in the VDDIO_NAND rail, brings down the
power from 9mW to 2mW.

Bug 630271

Tested Nand and EMMC boot up on whistler.

Change-Id: I98ac3c0ae237093b0f17552799e0beb956c735e9
Reviewed-on: http://git-master/r/822
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>

6 files changed, 66 insertions, 12 deletions

diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux.c
index 1729c98db64c..c883f84ee7b1 100644..100755
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux.c
@@ -322,6 +322,11 @@ void NvRmPrivAp15InitTrisateRefCount(NvRmDeviceHandle hDevice)
     NvOsMutexUnlock(hDevice->mutex);
 }
 
+void NvRmAp15SetDefaultTristate(NvRmDeviceHandle hDevice)
+{
+    return;
+}
+
 void NvRmPrivAp15SetGpioTristate(
     NvRmDeviceHandle hDevice,
     NvU32 Port,
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux_utils.h b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux_utils.h
index be1402f5d645..f9fd782a3315 100644..100755
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux_utils.h
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux_utils.h
@@ -101,6 +101,12 @@ extern "C"
                   APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_##RESOLUTIONMUX, \
                   APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_##CONFLICTMUX, \
                   PinMuxConfig_Unset))
+// TODO: Need to implement in PINMUX_DEBUG_MODE
+#define TRISTATE_UNUSED(PADGROUP, TRISTATE_REG) \
+        (PIN_MUX_ENTRY(((APB_MISC_PP_TRISTATE_REG_##TRISTATE_REG##_0 - APB_MISC_PP_TRISTATE_REG_A_0)>>2), \
+                APB_MISC_PP_TRISTATE_REG_##TRISTATE_REG##_0_Z_##PADGROUP##_SHIFT, \
+                0, 0, 0, 0, 0, -1))
+
 
 #if NVRM_PINMUX_DEBUG_FLAG
 #define CONFIG(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX) \
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c
index 8a2ac58efdf0..66459fcdc4c5 100644..100755
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c
@@ -1208,3 +1208,32 @@ NvRmAp20GetStraps(
     return NvSuccess;
 }
 
+static const NvU32 g_VddioNand[] = {
+    TRISTATE_UNUSED (ATA,A), TRISTATE_UNUSED (ATB,A), TRISTATE_UNUSED (ATC,A),
+    TRISTATE_UNUSED (ATD,A), TRISTATE_UNUSED (PTA,A), TRISTATE_UNUSED (GMA,A),
+    TRISTATE_UNUSED (GMC,A), TRISTATE_UNUSED (GMD,B), TRISTATE_UNUSED (GMB,B),
+    TRISTATE_UNUSED (ATE,B), TRISTATE_UNUSED (GME,B),
+};
+
+void NvRmAp20SetDefaultTristate(NvRmDeviceHandle hDevice)
+{
+    NvU32 Size = 0;
+    NvU32 TsOffs;
+    NvU32 TsShift ;
+    NvU32 i = 0;
+    Size = NV_ARRAY_SIZE(g_VddioNand) / sizeof(NvU32);
+    for ( i =0; i< Size; i++)
+    {
+        TsOffs = NV_DRF_VAL(MUX,ENTRY, TS_OFFSET, g_VddioNand[i]);
+        TsShift = NV_DRF_VAL(MUX,ENTRY, TS_SHIFT,  g_VddioNand[i]);
+        NvU32 Curr = NV_REGR(hDevice,
+             NvRmModuleID_Misc, 0 ,
+            APB_MISC_PP_TRISTATE_REG_A_0 + 4*TsOffs);
+        Curr &= ~(1<<TsShift);
+        Curr |= 1<<TsShift;
+
+        NV_REGW(hDevice, NvRmModuleID_Misc, 0 ,
+            APB_MISC_PP_TRISTATE_REG_A_0 + 4*TsOffs, Curr);
+    }
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c
index e60e4654a413..c4dafab658a8 100644..100755
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c
@@ -139,11 +139,11 @@ typedef struct
         NvRmDeviceHandle hDevice,
         NvRmStrapGroup StrapGroup,
         NvU32* pStrapValue);
+    void
+    (*pfnSetDefaultTristate)(
+        NvRmDeviceHandle hDevice);
 } NvPinmuxPrivMethods;
 
-static NvPinmuxPrivMethods* NvRmPrivGetPinmuxMethods(
-    NvRmDeviceHandle hDevice);
-
 static NvPinmuxPrivMethods* NvRmPrivGetPinmuxMethods(NvRmDeviceHandle hDevice)
 {
     static NvPinmuxPrivMethods *p;
@@ -159,7 +159,8 @@ static NvPinmuxPrivMethods* NvRmPrivGetPinmuxMethods(NvRmDeviceHandle hDevice)
         NvRmPrivAp15GetModuleInterfaceCaps,
         NvRmPrivAp15EnableExternalClockSource,
         NvRmPrivAp15GetExternalClockSourceFreq,
-        NvRmAp15GetStraps
+        NvRmAp15GetStraps,
+        NvRmAp15SetDefaultTristate
     };
     static NvPinmuxPrivMethods s_Ap16Methods =
     {
@@ -173,7 +174,8 @@ static NvPinmuxPrivMethods* NvRmPrivGetPinmuxMethods(NvRmDeviceHandle hDevice)
         NvRmPrivAp16GetModuleInterfaceCaps,
         NvRmPrivAp15EnableExternalClockSource,
         NvRmPrivAp15GetExternalClockSourceFreq,
-        NvRmAp15GetStraps
+        NvRmAp15GetStraps,
+        NvRmAp15SetDefaultTristate
     };
     static NvPinmuxPrivMethods s_Ap20Methods =
     {
@@ -187,7 +189,8 @@ static NvPinmuxPrivMethods* NvRmPrivGetPinmuxMethods(NvRmDeviceHandle hDevice)
         NvRmPrivAp20GetModuleInterfaceCaps,
         NvRmPrivAp20EnableExternalClockSource,
         NvRmPrivAp20GetExternalClockSourceFreq,
-        NvRmAp20GetStraps
+        NvRmAp20GetStraps,
+        NvRmAp20SetDefaultTristate
     };
 
     NV_ASSERT(hDevice);
@@ -292,6 +295,8 @@ void NvRmInitPinMux(
     NvBool First)
 {
     NvPinmuxPrivMethods *p = NvRmPrivGetPinmuxMethods(hDevice);
+    if (First)
+        (p->pfnSetDefaultTristate)(hDevice);
 
     if (!hDevice->PinMuxTable)
     {
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h
index e22baf53f10c..8614aecb5cb3 100644..100755
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h
@@ -310,6 +310,10 @@ NvRmPrivAp15SetGpioTristate(
     NvU32 Pin,
     NvBool EnableTristate);
 
+void NvRmAp15SetDefaultTristate (NvRmDeviceHandle hDevice);
+
+void NvRmAp20SetDefaultTristate (NvRmDeviceHandle hDevice);
+
 #ifdef __cplusplus
 }
 #endif  /* __cplusplus */
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
index 73f477e24e39..2221ef071261 100755
--- a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
@@ -887,7 +887,7 @@ NvOdmQueryDapPortGetConnectionTable(
 {
     static const NvOdmQueryDapPortConnection s_Property[] =
     {
-        { NvOdmDapConnectionIndex_Music_Path, 
+        { NvOdmDapConnectionIndex_Music_Path,
           2, { {NvOdmDapPort_I2s1, NvOdmDapPort_Dap1, NV_FALSE},
                {NvOdmDapPort_Dap1, NvOdmDapPort_I2s1, NV_TRUE} } },
     };
@@ -896,7 +896,7 @@ NvOdmQueryDapPortGetConnectionTable(
         { NvOdmDapConnectionIndex_Music_Path,
           2, { {NvOdmDapPort_I2s1, NvOdmDapPort_Dap1, NV_FALSE},
                {NvOdmDapPort_Dap1, NvOdmDapPort_I2s1, NV_TRUE} } },
-        
+
         // Voicecall without Bluetooth
         { NvOdmDapConnectionIndex_VoiceCall_NoBlueTooth,
           3, { {NvOdmDapPort_Dap3, NvOdmDapPort_Dap2, NV_FALSE},
@@ -916,7 +916,7 @@ NvOdmQueryDapPortGetConnectionTable(
     {
     case TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW:
         {
-            for( TableIndex = 0; 
+            for( TableIndex = 0;
                  TableIndex < NV_ARRAY_SIZE(s_Property_Ril_Emp_Rainbow); TableIndex++)
             {
                 if (s_Property_Ril_Emp_Rainbow[TableIndex].UseIndex == ConnectionIndex)
@@ -1061,13 +1061,18 @@ const NvU8* NvOdmQueryProjectName(void)
  // Pin attributes
  static const NvOdmPinAttrib s_pin_config_attributes[] = {
 
+   { NvOdmPinRegister_Ap20_PullUpDown_A,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_A(0x2, 0x2, 0x2, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0, 0x1, 0x0) },
     // Pull ups for the kbc pins
-    { NvOdmPinRegister_Ap20_PullUpDown_B,
-     NVODM_QUERY_PIN_AP20_PULLUPDOWN_B(0x0, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0) },
+   { NvOdmPinRegister_Ap20_PullUpDown_B,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_B(0x0, 0x0, 0x2, 0x0, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0) },
+
+   { NvOdmPinRegister_Ap20_PullUpDown_C,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_C(0x1, 0x1, 0x1, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0) },
 
     // Pull ups for the kbc pins
     { NvOdmPinRegister_Ap20_PullUpDown_E,
-     NVODM_QUERY_PIN_AP20_PULLUPDOWN_E(0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2) },
+      NVODM_QUERY_PIN_AP20_PULLUPDOWN_E(0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x2, 0x2) },
 
     // Set pad control for the sdio2 - - AOCFG1 and AOCFG2 pad control register
     { NvOdmPinRegister_Ap20_PadCtrl_AOCFG1PADCTRL,