diff options
| author | Vinayak Pane <vpane@nvidia.com> | 2011-12-10 18:28:34 -0800 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-02-15 14:13:37 -0800 |
| commit | f58bbb57b36fc02170d6905d07e573b414ac3021 (patch) | |
| tree | e847dec3e3cc8dcbebc39f9a712a6fdb47d1c02b | |
| parent | a81486774aadad68be9d58e5ac0caac55e3f35fd (diff) | |
arm: tegra: usb: Disable WAIT_FOR_VALID for hsic
The ehci generic port reset fails sometimes for HSIC modem
to connect in stress tests. HSIC bus reset apparently needs
a SW WAR. Using the feature of HS_READY_WAIT_FOR_VALID to disable
HSIC transmit config signal for HS ready wait for valid.
This is AP30 specific workaround.
Bug 898008
Bug 932606
Change-Id: I3d1aafa1bbd046769b0eb62970aa990ae7bad617
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/83279
Reviewed-by: Rajkumar Jayaraman <rjayaraman@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/usb_phy.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 69f1e0563926..7bb5e753b235 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -165,6 +165,9 @@ #define UHSIC_HSRX_CFG1 0x80c #define UHSIC_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) +#define UHSIC_TX_CFG0 0x810 +#define UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE (1 << 6) + #define UHSIC_MISC_CFG0 0x814 #define UHSIC_SUSPEND_EXIT_ON_EDGE (1 << 7) #define UHSIC_DETECT_SHORT_CONNECT (1 << 8) @@ -345,6 +348,9 @@ #define UHSIC_HSRX_CFG1 0xc0c #define UHSIC_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) +#define UHSIC_TX_CFG0 0xc10 +#define UHSIC_HS_READY_WAIT_FOR_VALID (1 << 9) + #define UHSIC_MISC_CFG0 0xc14 #define UHSIC_SUSPEND_EXIT_ON_EDGE (1 << 7) #define UHSIC_DETECT_SHORT_CONNECT (1 << 8) @@ -564,9 +570,6 @@ static u32 utmip_rctrl_val, utmip_tctrl_val; #define UHSIC_PLL_CFG0 0x800 -#define UHSIC_TX_CFG0 0x810 -#define UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE (1 << 6) - #define UHSIC_CMD_CFG0 0x824 #define UHSIC_PRETEND_CONNECT_DETECT (1 << 5) @@ -2200,6 +2203,13 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy, bool is_dpd) val |= UHSIC_HS_SYNC_START_DLY(uhsic_config->sync_start_delay); writel(val, base + UHSIC_HSRX_CFG1); +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + /* WAR HSIC TX */ + val = readl(base + UHSIC_TX_CFG0); + val &= ~UHSIC_HS_READY_WAIT_FOR_VALID; + writel(val, base + UHSIC_TX_CFG0); +#endif + val = readl(base + UHSIC_MISC_CFG0); val |= UHSIC_SUSPEND_EXIT_ON_EDGE; #ifdef CONFIG_ARCH_TEGRA_3x_SOC |