diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2014-05-21 12:57:04 +0530 |
|---|---|---|
| committer | Matthew Pedro <mapedro@nvidia.com> | 2015-07-23 08:14:37 -0700 |
| commit | 8770f6279885cd7c769a09e32ce051c5e61311ad (patch) | |
| tree | 5c0d3c79c990eaaf6f1ae06d92451016408006df | |
| parent | 350e11af044e460b6ec6afa649214d040ccf37ae (diff) | |
arm: tegra: headsmp: fix tegra_with_secure_firmware access with MMU off
There are places during the CPU resume path where we access this variable
with MMU off. In such scenarios we should use the physical address for this
variable.
This fixes the virtualisation team's issue, since they were the ones who
reported it in the first place. Fix a case where the code running from
iRAM was accessing the variable from DRAM instead of the one cached in
iRAM.
Bug 1411345
Change-Id: I9005c30329d38bae305a4a7b31ae7e2ca83e8a5d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/412540
(cherry picked from commit a0553bb8f3fa7c76c2c0a6528d0c106ee22c7a59)
Reviewed-on: http://git-master/r/771679
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 33 |
1 files changed, 14 insertions, 19 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 5558510c95bf..211521055116 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -50,12 +50,13 @@ */ __CPUINIT ENTRY(tegra_secondary_startup) + ldr r0, =tegra_with_secure_firmware + sub r0, #(PAGE_OFFSET - TEGRA_DRAM_BASE) + ldr r12, [r0] + bl __invalidate_cpu_state - ldr r0, =tegra_with_secure_firmware - sub r0, #PAGE_OFFSET - ldr r0, [r0] - cmp r0, #1 + cmp r12, #1 @ secure firmware present? beq secondary_startup /* enable user space perf counter access */ @@ -85,10 +86,10 @@ ENDPROC(tegra_secondary_startup) * re-enabling sdram. */ ENTRY(tegra_resume) - ldr r1, =tegra_with_secure_firmware - sub r1, #PAGE_OFFSET - ldr r1, [r1] - cmp r1, #1 + ldr r0, =tegra_with_secure_firmware + sub r0, #(PAGE_OFFSET - TEGRA_DRAM_BASE) + ldr r12, [r0] + cmp r12, #1 bne cpu_not_secure mov32 r1, TEGRA_TMRUS_BASE @@ -129,9 +130,7 @@ cpu_not_secure: #ifdef CONFIG_CACHE_L2X0 #if !defined(CONFIG_ARCH_TEGRA_14x_SOC) - ldr r1, =tegra_with_secure_firmware - ldr r1, [r1] - cmp r1, #1 + cmp r12, #1 @ secure firmware present? beq cpu_resume adr r0, tegra_resume_l2_init @@ -240,10 +239,7 @@ __invalidate_cpu_state: teq r1, r0 beq cortex_a9 - ldr r0, =tegra_with_secure_firmware - sub r0, #PAGE_OFFSET - ldr r0, [r0] - cmp r0, #1 + cmp r12, #1 @ secure firmware present? beq __enable_i_cache_branch_pred mrc p15, 0x1, r0, c15, c0, 3 @ L2 prefetch control reg @@ -391,10 +387,9 @@ ENTRY(__tegra_cpu_reset_handler) b . #endif - ldr r0, =tegra_with_secure_firmware - sub r0, #PAGE_OFFSET - ldr r0, [r0] - cmp r0, #1 + adr r12, __tegra_cpu_reset_handler_data + ldr r7, [r12, #RESET_DATA(SECURE_FW_PRESENT)] + cmp r7, #1 @ if !secure beq cpu_is_secure cpsid aif, 0x13 @ SVC mode, interrupts disabled |