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authorPreetham Chandru <pchandru@nvidia.com>2011-09-08 20:43:56 +0530
committerVarun Colbert <vcolbert@nvidia.com>2011-09-09 18:59:41 -0700
commit61313ed2494424513cb6e42c22cb7ca31f21473e (patch)
treefc415056a660ff0c27a21a0428b660a27da1b21c
parent8217615021a6ffeb992327f6b010ea9deebc34e7 (diff)
ARM: tegra2: clock: Update bus operations
Relaxed bus set rate success condition: instead of checking for the exact rate check for the closest rate. This makes bus clocks configurable from sources/PLLs with variable frequencies. Bug: 869054 Change-Id: I58edd6ab794f3699b3451ba82080abf76cace2ad Signed-off-by: Preetham Chandru <pchandru@nvidia.com> Reviewed-on: http://git-master/r/50747 Reviewed-by: Allen Martin <amartin@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 6a1cc9b826e6..319655920e3d 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -538,7 +538,7 @@ static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
unsigned long parent_rate = clk_get_rate(c->parent);
int i;
for (i = 1; i <= 4; i++) {
- if (rate == parent_rate / i) {
+ if (rate >= parent_rate / i) {
val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
val |= (i - 1) << c->reg_shift;
clk_writel(val, c->reg);