diff options
author | Max Krummenacher <max.krummenacher@toradex.com> | 2018-08-13 14:20:51 +0200 |
---|---|---|
committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-06-21 17:22:04 +0200 |
commit | 723ff1e54512913416c790a8e870ef7c0c54977d (patch) | |
tree | 044b590d0939b002cc87f3c85c454bc272619125 | |
parent | bfa9da84676269cd86a3e8d42c6c0d267712aa0e (diff) |
arm64: dts: fsl: colibri-imx8qxp: add initial device tree
Copied from toradex_imx_4.14.78_1.0.0_ga-bring_up.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
7 files changed, 1707 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 4b2db1b70f3e..9f95685cfb5f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -92,7 +92,11 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \ fsl-imx8qxp-ddr3l-val.dtb \ fsl-imx8dx-17x17-val.dtb \ fsl-imx8dx-lpddr4-arm2.dtb \ - fsl-imx8dxp-lpddr4-arm2.dtb + fsl-imx8dxp-lpddr4-arm2.dtb \ + fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb \ + fsl-imx8qxp-colibri-eval-v3.dtb \ + fsl-imx8qxp-colibri-lvds-dual-eval-v3.dtb \ + fsl-imx8qxp-colibri-lvds-single-eval-v3.dtb dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \ fsl-imx8mq-ddr4-arm2.dtb \ fsl-imx8mq-ddr4-arm2-gpmi-nand.dtb \ diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index e4ef0d0154a8..45f5eee437e7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -2403,6 +2403,7 @@ adc0: adc@5a880000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x0 0x5a880000 0x0 0x10000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; @@ -2720,6 +2721,118 @@ power-domains = <&pd_mipi_csi>; }; + pwm0: pwm@5d000000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d000000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM0_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM0_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM0_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm0>; + status = "disabled"; + }; + + pwm1: pwm@5d010000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d010000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM1_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM1_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM1_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm1>; + status = "disabled"; + }; + + pwm2: pwm@5d020000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d020000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM2_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM2_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM2_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm2>; + status = "disabled"; + }; + + pwm3: pwm@5d030000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d030000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM3_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM3_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM3_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm3>; + status = "disabled"; + }; + + pwm4: pwm@5d040000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d040000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM4_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM4_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM4_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm4>; + status = "disabled"; + }; + + pwm5: pwm@5d050000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d050000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM5_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM5_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM5_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm5>; + status = "disabled"; + }; + + pwm6: pwm@5d060000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d060000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM6_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM6_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM6_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm6>; + status = "disabled"; + }; + + pwm7: pwm@5d070000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d070000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM7_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM7_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM7_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm7>; + status = "disabled"; + }; + gpu_3d0: gpu@53100000 { compatible = "fsl,imx8-gpu"; reg = <0x0 0x53100000 0 0x40000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts new file mode 100644 index 000000000000..6a91caaaaeac --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; +//#define IS_A0_SILICON +//#define DSI_TO_HDMI_V10 + +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP with LT8912 MIPI-DSI 2 HDMI bridge"; + compatible = "toradex,colibri-imx8qxp-dsihdmi-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + +}; + +/* DSI/LVDS port 0 */ +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + +#ifndef DSI_TO_HDMI_V10 + /* DSI to HDMI Adapter V1.1A */ + i2c-switch@70 { + compatible = "nxp,pca9540"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* DDC/EDID */ + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + lt8912@48 { + compatible = "lontium,lt8912"; + reg = <0x48>; + + port { + lt8912_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + + display-timings { + native-mode = <&timing1>; + + timing0: timing0 { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <720>; + hfront-porch = <110>; + hsync-len = <40>; + hback-porch = <220>; + vfront-porch = <5>; + vsync-len = <5>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing1: timing1 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <88>; + hsync-len = <44>; + hback-porch = <148>; + vfront-porch = <36>; + vsync-len = <5>; + vback-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + }; + }; +#else /* DSI_TO_HDMI_V10 */ + /* DSI to HDMI Adapter V1.0A */ + lt8912@48 { + compatible = "lontium,lt8912"; + reg = <0x48>; + + port { + lt8912_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + + display-timings { + native-mode = <&timing1>; + + timing0: timing0 { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <720>; + hfront-porch = <110>; + hsync-len = <40>; + hback-porch = <220>; + vfront-porch = <5>; + vsync-len = <5>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing1: timing1 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <88>; + hsync-len = <44>; + hback-porch = <148>; + vfront-porch = <36>; + vsync-len = <5>; + vback-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +#endif /* DSI_TO_HDMI_V10 */ +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "disabled"; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + pwr-delay = <10>; + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_out: endpoint { + remote-endpoint = <<8912_1_in>; + }; + }; +}; + +/* DSI/LVDS port 1 */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_csi>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "disabled"; +}; + +&mipi_dsi2 { + pwr-delay = <10>; + status = "disabled "; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts new file mode 100644 index 000000000000..1a0bdf1240d2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; +//#define IS_A0_SILICON + +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP"; + compatible = "toradex,colibri-imx8qxp-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; /* BKL1_ON */ + pwms = <&pwm_adma_lcdif 0 100000 PWM_POLARITY_INVERTED>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + display-subsystem { + status = "disabled"; + }; + + panel { + compatible = "edt,et070080dh6"; + backlight = <&backlight>; + + port { + lcd_panel_in: endpoint { +// remote-endpoint = <&lcdif_out>; + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; +#if 1 + lcd_display: disp0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "bgr666"; + + port@0 { + reg = <0>; + lcd_display_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + port@1 { + reg = <1>; + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; +#endif + +}; + +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + port@0 { + lcdif_out: lcdif-endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +/* DSI/LVDS port 0 */ +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; +}; + +&mipi_dsi_phy1 { + status = "disabled"; +}; + +&mipi_dsi1 { + pwr-delay = <10>; + status = "disabled"; +}; + +&mipi_dsi_bridge1 { + status = "disabled"; +}; + +/* DSI/LVDS port 1 */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_csi>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + }; +}; + +&mipi_dsi_phy2 { + status = "disabled"; +}; + +&mipi_dsi2 { + pwr-delay = <10>; + status = "disabled "; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + +&pwm_adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_a>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi new file mode 100644 index 000000000000..bc2c66d8d3f4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi @@ -0,0 +1,955 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +#include "fsl-imx8qxp.dtsi" + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + chosen { + bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200"; + stdout-path = &lpuart3; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det &pinctrl_ext_io0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx8qxp-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + /*simple-audio-card,mclk-fs = <1>;*/ + + simple-audio-card,cpu { + sound-dai = <&sai0>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>; + + colibri-imx8qxp { + pinctrl_ad7879_int: ad7879-int { /* TOUCH Interrupt */ + fsl,pins = < + SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x00000021 + >; + }; + + pinctrl_adc0: adc0grp { + fsl,pins = < + SC_P_ADC_IN0_ADMA_ADC_IN0 0x60 + SC_P_ADC_IN1_ADMA_ADC_IN1 0x60 + SC_P_ADC_IN4_ADMA_ADC_IN4 0x60 + SC_P_ADC_IN5_ADMA_ADC_IN5 0x60 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 + SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */ + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x00000020 /* CTS */ + SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x00000020 /* RTS */ + SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x00000020 /* DSR */ + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000020 /* DCD */ + SC_P_CSI_EN_LSIO_GPIO3_IO02 0x00000020 /* RI */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061 + >; + }; + + pinctrl_fec1_sleep: fec1-sleep-grp { + fsl,pins = < + SC_P_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 + SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000041 + SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x00000041 + SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x00000041 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000041 + SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x00000041 + SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x00000041 + SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x00000041 + SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x00000041 + >; + }; + + pinctrl_gpio_bl_on: gpio-bl-on { + fsl,pins = < + SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x00000040 + >; + }; + + pinctrl_hog0: hog0grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ + >; + }; + + pinctrl_hog1: hog1grp { + fsl,pins = < + SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x00000020 /* 45 */ + SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* 65 */ + SC_P_CSI_D07_CI_PI_D09 0x00000061 + SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x00000020 /* 69 */ + SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000020 /* 73 */ + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x00000020 /* 79 */ + SC_P_CSI_D02_CI_PI_D04 0x00000061 + SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* 85 */ + SC_P_CSI_D06_CI_PI_D08 0x00000061 + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x00000020 /* 95 */ + SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x00000020 /* 97 */ + SC_P_CSI_D03_CI_PI_D05 0x00000061 + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x00000020 /* 99 */ + SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x00000020 /* 101 */ + SC_P_CSI_D00_CI_PI_D02 0x00000061 + SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x00000020 /* 103 */ + SC_P_CSI_D01_CI_PI_D03 0x00000061 + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x00000020 /* 105 */ + SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x00000020 /* 107 */ + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x00000020 /* 127 */ + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x00000020 /* 131 */ + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000020 /* 133 */ + SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x00000020 /* 96 */ + SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x00000020 /* 98 */ + SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000020 /* 100 */ + SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000020 /* 102 */ + SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x00000020 /* 104 */ + SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000020 /* 106 */ + >; + }; + + pinctrl_hog2: hog2grp { + fsl,pins = < + SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x00000020 /* 75 */ + SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x00000020 /* 77 */ + SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000020 /* 89 */ + SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x00000020 /* 93 */ + >; + }; + + /* This pin is used in the SCFW as a UART. Using it from + * Linux would require rewritting the SCFW board file. + */ + pinctrl_hog_scfw: hogscfwgrp { + fsl,pins = < + SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x00000020 /* 144 */ + >; + }; + + /* On Module I2C */ + pinctrl_i2c0: i2c0grp { + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 + SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 + >; + }; + + /* Off Module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 + SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_pcieb: pciebgrp { + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x00000060 + >; + }; + + pinctrl_pwm_a: pwma { + /* both pins are connected together, reserve the unused CSI_D05 */ + fsl,pins = < + SC_P_CSI_D05_CI_PI_D07 0x00000061 + SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000060 + >; + }; + + pinctrl_pwm_b: pwmb { + fsl,pins = < + SC_P_UART1_TX_LSIO_PWM0_OUT 0x00000060 + >; + }; + + pinctrl_pwm_c: pwmc { + fsl,pins = < + SC_P_UART1_RX_LSIO_PWM1_OUT 0x00000060 + >; + }; + + pinctrl_pwm_d: pwmd { + /* both pins are connected together, reserve the unused CSI_D04 */ + fsl,pins = < + SC_P_CSI_D04_CI_PI_D06 0x00000061 + SC_P_UART1_RTS_B_LSIO_PWM2_OUT 0x00000060 + >; + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + SC_P_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 + SC_P_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 + SC_P_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 + SC_P_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + pinctrl_sgtl5000: sgtl5000 { + fsl,pins = < + /* MIC GND EN */ + SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x00000041 + >; + }; + + pinctrl_sgtl5000_usb_clk: sgtl5000-usb-clk { + fsl,pins = < + SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x00000021 + >; + }; + + /*INT*/ + pinctrl_usb3503a: usb3503a-grp { + fsl,pins = < + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061 + >; + }; + + pinctrl_usbc_det: usbc-det { + fsl,pins = < + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 + >; + }; + + pinctrl_ext_io0: ext-io0 { + fsl,pins = < + SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 + >; + }; + + pinctrl_lcdif: lcdif-pins { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000060 + + SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000060 + SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 + SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 + SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 + SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 + SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 + SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 + SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 + SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 + SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 + SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 + SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 + SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 + SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 + SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 + SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 + SC_P_SPI3_CS1_ADMA_LCDIF_D16 0x00000060 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000060 + SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 + >; + }; + + pinctrl_usbh1_reg: usbh1-reg { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +#if 0 + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c + >; + }; +#endif + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_csi: mipi_csi_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_lpspi2: lpspi2 { + fsl,pins = < + SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x00000021 + SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 + SC_P_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 + SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x00000020 + >; + }; + }; +}; + +#ifndef IS_A0_SILICON +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; +#endif + +/* CAN on UART_B RTS/CTS */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_module_3v3>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_module_3v3>; + status = "okay"; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&pd_dma_lpuart3 { + debug_console; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&pixel_combiner { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +/* Display Prefetch Resolve, (Tiling) */ +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, + <&clk IMX8QXP_ENET0_AHB_CLK>, + <&clk IMX8QXP_ENET0_REF_50MHZ_CLK>, + <&clk IMX8QXP_ENET0_PTP_CLK>, + <&clk IMX8QXP_ENET0_TX_CLK>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; +#if 0 +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; +#endif + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; + status = "okay"; + + /* IMX8QXP_AUD_MCLKOUT0 is used by both the usb3803 and sgtl5000 + So do the pinmuxing and setup for both here */ + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; + + /* USB3503A */ + usb3803@08 { + compatible = "smsc,usb3803"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503a>; + reg = <0x08>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "refclk"; + power-domains = <&pd_mclk_out0>; + bypass-gpios = <&gpio_expander_43 5 GPIO_ACTIVE_LOW>; + intn-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio_expander_43 4 GPIO_ACTIVE_LOW>; + disabled-ports = <2>; + initial-mode = <1>; + non-removable-devices = <1>; + }; + + /* SGTL5000 */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + power-domains = <&pd_mclk_out0>; + VDDA-supply = <®_module_3v3_avdd>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <®_vref_1v8>; + }; + + /* GPIO expander */ + gpio_expander_43: gpio-expander@43 { + compatible = "fcs,fxl6408"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x43>; + inital_io_dir = <0xff>; + inital_output = <0x05>; + }; + + /* Touch controller */ + ad7879@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&gpio3>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&pcieb{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>; + ext_osc = <1>; + clkreq-gpio = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>; + disable-gpio = <&gpio_expander_43 6 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio_expander_43 2 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; +/* epdev_on-supply = <®_wifi>;*/ + fsl,max-link-speed = <1>; + status = "okay"; +}; + +&pwm_adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_a>; + status = "okay"; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_b>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_c>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_d>; + status = "okay"; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +&sai0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&tsens { + tsens-num = <3>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 2>; + + trips { + pmic_alert0: trip0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_module_3v3>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +&vpu { + status = "disabled"; +}; + +#ifdef IS_A0_SILICON +&vpu_decoder { + status = "disabled"; +}; + +&vpu_encoder { + status = "disabled"; +}; +#else +&vpu_decoder { + core_type = <1>; + status = "okay"; +}; + +&vpu_encoder { + core_type = <1>; + status = "okay"; +}; +#endif diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts new file mode 100644 index 000000000000..3171b7ef7d5a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; +//#define IS_A0_SILICON + +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP with dual channel lvds"; + compatible = "toradex,colibri-imx8qxp-lvds-dual-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bklght_on>; + enable-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; /* Ext.Conn 25: LVDS1_GPIO0_00 */ + pwms = <&pwm_adma_lcdif 0 5000000>; /* PWM freq. 200Hz */ + brightness-levels = <0 8 16 32 64 128 192 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + lvds1_panel { + compatible = "lg,lp156wf1"; + backlight = <&backlight>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + pinctrl_gpio_bklght_on: gpio-bl-on { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x00000020 + >; + }; + }; +}; + +/* DSI/LVDS port 0 */ +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_1_dual_lvds>; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; /* Actually would need 18 but isn't supported by the driver */ + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + pwr-delay = <10>; + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "disabled"; +}; + +/* DSI/LVDS port 1 */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_csi>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + pwr-delay = <10>; + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts new file mode 100644 index 000000000000..09c267e0dc98 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; +//#define IS_A0_SILICON + +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP with single channel lvds"; + compatible = "toradex,colibri-imx8qxp-lvds-single-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bklght_on>; + enable-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; /* Ext.Conn 25: LVDS1_GPIO0_00 */ + pwms = <&pwm_adma_lcdif 0 5000000>; /* PWM freq. 200Hz */ + brightness-levels = <255 192 128 64 32 16 8 0>; + default-brightness-level = <6>; + status = "okay"; + }; + + lvds1_panel { + compatible = "toradex,captouch-101-lvds"; + backlight = <&backlight>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + pinctrl_touch: touchgrp { + fsl,pins = < + SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x06000040 + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x06000040 + >; + }; + + pinctrl_gpio_bklght_on: gpio-bl-on { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x00000020 + >; + }; + }; +}; + +/* DSI/LVDS port 0 */ +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; /* Actually would need 18 but isn't supported by the driver */ + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + pwr-delay = <10>; + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "disabled"; +}; + +/* DSI/LVDS port 1 */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_csi>; + clock-frequency = <100000>; + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "disabled"; +}; + +&mipi_dsi2 { + pwr-delay = <10>; + status = "disabled"; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + +&i2c1 { + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + reg = <0x4a>; + interrupt-parent = <&gpio3>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 98 */ + reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; /* SODIMM 133 */ + status = "okay"; + }; +}; |