video: tegra: host: Sync Tegra11 gr3d with Tegra3

Tegra3 gr3d context switching has some fixes and changes that do not
exist yet in Tegra11:

 * FDC flush
 * Dynamic syncpt id
 * Usage of constant instead of magic numbers in reg names
 * Removal of __init on non-init functions
 * ISP channel has sync points listed
 * 2D submits are serialized
 * Some clock rates were misaligned
 * Some #include rearrangement and white space alignment

Change-Id: Id7c917a137ebf510206a94abbb7ceb1aa563a643
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/129950
Reviewed-by: Automatic_Commit_Validation_User

4 files changed, 70 insertions, 56 deletions

diff --git a/drivers/video/tegra/host/gr3d/gr3d.h b/drivers/video/tegra/host/gr3d/gr3d.h
index 61f708cea95c..c6bcf66f76d1 100644
--- a/drivers/video/tegra/host/gr3d/gr3d.h
+++ b/drivers/video/tegra/host/gr3d/gr3d.h
@@ -35,6 +35,7 @@
 #define AR3D_GSHIM_WRITE_MASK 0xb00
 #define AR3D_GSHIM_READ_SELECT 0xb01
 #define AR3D_GLOBAL_MEMORY_OUTPUT_READS 0xe40
+#define AR3D_PIPEALIAS_DW_MEMORY_OUTPUT_DATA 0xc10
 
 struct nvhost_hwctx;
 struct nvhost_channel;
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t114.c b/drivers/video/tegra/host/gr3d/gr3d_t114.c
index 9143a64886b7..ef4cb39e0ab9 100644
--- a/drivers/video/tegra/host/gr3d/gr3d_t114.c
+++ b/drivers/video/tegra/host/gr3d/gr3d_t114.c
@@ -21,11 +21,10 @@
  */
 
 #include "nvhost_hwctx.h"
+#include "nvhost_channel.h"
 #include "dev.h"
 #include "host1x/host1x02_hardware.h"
-#include "host1x/host1x_syncpt.h"
-#include "gr3d/gr3d.h"
-#include "nvhost_channel.h"
+#include "gr3d.h"
 #include "chip_support.h"
 #include "nvhost_memmgr.h"
 #include "scale3d.h"
@@ -117,15 +116,25 @@ static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma)
 	nvhost_cdma_push(cdma,
 			nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
 					host1x_uclass_wait_syncpt_base_r(), 1),
-			nvhost_class_host_wait_syncpt_base(NVSYNCPT_3D,
+			nvhost_class_host_wait_syncpt_base(p->syncpt,
 							p->waitbase, 1));
 	/* back to 3d */
 	nvhost_cdma_push(cdma,
 			nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
-			nvhost_opcode_imm(0xe40, 1));
+			NVHOST_OPCODE_NOOP);
+
+	/* invalidate the FDC to prevent cache-coherency issues across GPUs
+	   note that we assume FDC_CONTROL_0 is left in the reset state by all
+	   contexts.  the invalidate bit will clear itself, so the register
+	   should be unchanged after this */
+	nvhost_cdma_push(cdma,
+		nvhost_opcode_imm(AR3D_FDC_CONTROL_0,
+			AR3D_FDC_CONTROL_0_RESET_VAL
+				| AR3D_FDC_CONTROL_0_INVALIDATE),
+		nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 1));
 	nvhost_cdma_push(cdma,
-			nvhost_opcode_nonincr(0x904, 1),
-			ctx->restore_phys);
+		nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_ADDRESS, 1),
+		ctx->restore_phys);
 	/* gather the save buffer */
 	nvhost_cdma_push_gather(cdma,
 			nvhost_get_host(nctx->channel->dev)->memmgr,
@@ -135,17 +144,19 @@ static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma)
 			p->save_phys);
 }
 
-static void __init save_begin_v1(struct host1x_hwctx_handler *p, u32 *ptr)
+static void save_begin_v1(struct host1x_hwctx_handler *p, u32 *ptr)
 {
-	ptr[0] = nvhost_opcode_nonincr(0xc10, RESTORE_BEGIN_SIZE);
+	ptr[0] = nvhost_opcode_nonincr(AR3D_PIPEALIAS_DW_MEMORY_OUTPUT_DATA,
+			RESTORE_BEGIN_SIZE);
 	nvhost_3dctx_restore_begin(p, ptr + 1);
 	ptr += RESTORE_BEGIN_SIZE;
 }
 
-static void __init save_direct_v1(u32 *ptr, u32 start_reg, u32 count,
+static void save_direct_v1(u32 *ptr, u32 start_reg, u32 count,
 			u32 rst_reg)
 {
-	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0xc10, 1);
+	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID,
+			AR3D_PIPEALIAS_DW_MEMORY_OUTPUT_DATA, 1);
 	nvhost_3dctx_restore_direct(ptr + 1, rst_reg, count);
 	ptr += RESTORE_DIRECT_SIZE;
 	ptr[1] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
@@ -156,12 +167,13 @@ static void __init save_direct_v1(u32 *ptr, u32 start_reg, u32 count,
 	ptr[3] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count);
 }
 
-static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset,
+static void save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset,
 			u32 data_reg, u32 count,
 			u32 rst_reg, u32 rst_data_reg)
 {
 	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
-	ptr[1] = nvhost_opcode_nonincr(0xc10, RESTORE_INDIRECT_SIZE);
+	ptr[1] = nvhost_opcode_nonincr(AR3D_PIPEALIAS_DW_MEMORY_OUTPUT_DATA,
+			RESTORE_INDIRECT_SIZE);
 	nvhost_3dctx_restore_indirect(ptr + 2, rst_reg, offset, rst_data_reg,
 			count);
 	ptr += RESTORE_INDIRECT_SIZE;
@@ -173,14 +185,16 @@ static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset,
 	ptr[5] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count);
 }
 
-static void __init save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr)
+static void save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr)
 {
 	/* write end of restore buffer */
-	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0xc10, 1);
+	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID,
+			AR3D_PIPEALIAS_DW_MEMORY_OUTPUT_DATA, 1);
 	nvhost_3dctx_restore_end(p, ptr + 1);
 	ptr += RESTORE_END_SIZE;
 	/* op_done syncpt incr to flush FDC */
-	ptr[1] = nvhost_opcode_imm_incr_syncpt(host1x_uclass_incr_syncpt_cond_op_done_v(), p->syncpt);
+	ptr[1] = nvhost_opcode_imm_incr_syncpt(
+			host1x_uclass_incr_syncpt_cond_op_done_v(), p->syncpt);
 	/* host wait for that syncpt incr, and advance the wait base */
 	ptr[2] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
 			host1x_uclass_wait_syncpt_base_r(),
@@ -194,12 +208,12 @@ static void __init save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr)
 	/* set class back to 3d */
 	ptr[5] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
 	/* send reg reads back to host */
-	ptr[6] = nvhost_opcode_imm(0xe40, 0);
+	ptr[6] = nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 0);
 	/* final syncpt increment to release waiters */
 	ptr[7] = nvhost_opcode_imm(0, p->syncpt);
 }
 
-static void __init setup_save_regs(struct save_info *info,
+static void setup_save_regs(struct save_info *info,
 			const struct hwctx_reginfo *regs,
 			unsigned int nr_regs)
 {
@@ -262,7 +276,7 @@ static void __init setup_save_regs(struct save_info *info,
 	info->restore_count = restore_count;
 }
 
-static void __init setup_save(struct host1x_hwctx_handler *p, u32 *ptr)
+static void setup_save(struct host1x_hwctx_handler *p, u32 *ptr)
 {
 	struct save_info info = {
 		ptr,
@@ -310,7 +324,7 @@ static struct nvhost_hwctx *ctx3d_alloc_v1(struct nvhost_hwctx_handler *h,
 		return NULL;
 }
 
-struct nvhost_hwctx_handler * __init nvhost_gr3d_t114_ctxhandler_init(
+struct nvhost_hwctx_handler *nvhost_gr3d_t114_ctxhandler_init(
 		u32 syncpt, u32 waitbase,
 		struct nvhost_channel *ch)
 {
@@ -331,7 +345,7 @@ struct nvhost_hwctx_handler * __init nvhost_gr3d_t114_ctxhandler_init(
 
 	p->save_buf = mem_op().alloc(memmgr, p->save_size * 4, 32,
 				mem_mgr_flag_write_combine);
-	if (IS_ERR(p->save_buf)) {
+	if (IS_ERR_OR_NULL(p->save_buf)) {
 		p->save_buf = NULL;
 		return NULL;
 	}
diff --git a/drivers/video/tegra/host/gr3d/gr3d_t114.h b/drivers/video/tegra/host/gr3d/gr3d_t114.h
index 9b1798ee20e9..ed66cb19f27e 100644
--- a/drivers/video/tegra/host/gr3d/gr3d_t114.h
+++ b/drivers/video/tegra/host/gr3d/gr3d_t114.h
@@ -25,6 +25,7 @@
 
 struct nvhost_hwctx_handler;
 struct nvhost_device;
+struct nvhost_channel;
 
 struct nvhost_hwctx_handler *nvhost_gr3d_t114_ctxhandler_init(
 		u32 syncpt, u32 base,
diff --git a/drivers/video/tegra/host/t114/t114.c b/drivers/video/tegra/host/t114/t114.c
index 97f9dd4dcb2f..d7bcd8c24abb 100644
--- a/drivers/video/tegra/host/t114/t114.c
+++ b/drivers/video/tegra/host/t114/t114.c
@@ -1,45 +1,41 @@
 /*
  * drivers/video/tegra/host/t114/t114.c
  *
- * Tegra Graphics Init for T114 Architecture Chips
+ * Tegra Graphics Init for Tegra11 Architecture Chips
  *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
  *
- * This program is distributed in the hope that it will be useful, but WITHOUT
+ * This program is distributed in the hope it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/init.h>
 #include <linux/mutex.h>
+#include <linux/kernel.h>
+#include <linux/nvhost_ioctl.h>
 #include <mach/powergate.h>
 #include <mach/iomap.h>
-#include "dev.h"
-#include "host1x/host1x_cdma.h"
 #include "t20/t20.h"
 #include "t30/t30.h"
 #include "t114.h"
-#include "host1x/host1x02_hardware.h"
-#include "host1x/host1x_syncpt.h"
-#include "gr3d/gr3d.h"
 #include "gr3d/gr3d_t114.h"
 #include "gr3d/scale3d.h"
+#include "host1x/host1x02_hardware.h"
 #include "msenc/msenc.h"
 #include "tsec/tsec.h"
-#include <linux/nvhost_ioctl.h>
+#include "host1x/host1x.h"
+#include "chip_support.h"
 #include "nvhost_channel.h"
 #include "nvhost_memmgr.h"
-#include "chip_support.h"
+#include "host1x/host1x_syncpt.h"
 
 #define NVMODMUTEX_2D_FULL   (1)
 #define NVMODMUTEX_2D_SIMPLE (2)
@@ -51,8 +47,6 @@
 #define NVMODMUTEX_VI        (8)
 #define NVMODMUTEX_DSI       (9)
 
-#define HOST_EMC_FLOOR 300000000
-
 static int t114_num_alloc_channels = 0;
 
 static struct resource tegra_host1x02_resources[] = {
@@ -133,7 +127,7 @@ static struct nvhost_device tegra_gr3d03_device = {
 	.modulemutexes = BIT(NVMODMUTEX_3D),
 	.class	       = NV_GRAPHICS_3D_CLASS_ID,
 	.clocks = {{"gr3d", UINT_MAX},
-			{"emc", HOST_EMC_FLOOR} },
+			{"emc", UINT_MAX} },
 	.powergate_ids = { TEGRA_POWERGATE_3D, -1 },
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
 	.can_powergate = true,
@@ -150,11 +144,12 @@ static struct nvhost_device tegra_gr2d03_device = {
 	.modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
 			 BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
 	.clocks = {{"gr2d", 0},
-			{"epp", UINT_MAX},
-			{"emc", HOST_EMC_FLOOR} },
+			{"epp", 0},
+			{"emc", 300000000} },
 	NVHOST_MODULE_NO_POWERGATE_IDS,
-	NVHOST_DEFAULT_CLOCKGATE_DELAY,
-	.moduleid      = NVHOST_MODULE_NONE,
+	.clockgate_delay = 0,
+	.moduleid	= NVHOST_MODULE_NONE,
+	.serialize	= true,
 };
 
 static struct resource isp_resources[] = {
@@ -167,15 +162,18 @@ static struct resource isp_resources[] = {
 };
 
 static struct nvhost_device tegra_isp01_device = {
-	.name	 = "isp",
-	.id      = -1,
-	.resource = isp_resources,
-	.num_resources = ARRAY_SIZE(isp_resources),
-	.index   = 3,
-	.syncpts = 0,
+	.name		= "isp",
+	.id		= -1,
+	.resource	= isp_resources,
+	.num_resources	= ARRAY_SIZE(isp_resources),
+	.index		= 3,
+	.syncpts	= BIT(NVSYNCPT_VI_ISP_2) | BIT(NVSYNCPT_VI_ISP_3) |
+			  BIT(NVSYNCPT_VI_ISP_4),
+	.clocks		= { {"epp", 0} },
+	.keepalive	= true,
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
-	.moduleid      = NVHOST_MODULE_ISP,
+	.moduleid	= NVHOST_MODULE_ISP,
 };
 
 static struct resource vi_resources[] = {
@@ -189,9 +187,9 @@ static struct resource vi_resources[] = {
 
 static struct nvhost_device tegra_vi01_device = {
 	.name	       = "vi",
-	.id            = -1,
 	.resource      = vi_resources,
 	.num_resources = ARRAY_SIZE(vi_resources),
+	.id            = -1,
 	.index         = 4,
 	.syncpts       = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
 			 BIT(NVSYNCPT_VI_ISP_0) | BIT(NVSYNCPT_VI_ISP_1) |
@@ -225,7 +223,7 @@ static struct nvhost_device tegra_msenc02_device = {
 	.class	       = NV_VIDEO_ENCODE_MSENC_CLASS_ID,
 	.exclusive     = false,
 	.keepalive     = true,
-	.clocks = {{"msenc", UINT_MAX}, {"emc", HOST_EMC_FLOOR} },
+	.clocks = {{"msenc", UINT_MAX}, {"emc", 300000000} },
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
 	.moduleid      = NVHOST_MODULE_MSENC,
@@ -263,7 +261,7 @@ static struct nvhost_device tegra_tsec01_device = {
 	.waitbases     = BIT(NVWAITBASE_TSEC),
 	.class         = NV_TSEC_CLASS_ID,
 	.exclusive     = false,
-	.clocks = {{"tsec", UINT_MAX}, {"emc", HOST_EMC_FLOOR} },
+	.clocks = {{"tsec", UINT_MAX}, {"emc", 300000000} },
 	NVHOST_MODULE_NO_POWERGATE_IDS,
 	NVHOST_DEFAULT_CLOCKGATE_DELAY,
 	.moduleid      = NVHOST_MODULE_TSEC,