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authorShengjiu Wang <shengjiu.wang@freescale.com>2017-07-12 18:02:35 +0800
committerJason Liu <jason.hui.liu@nxp.com>2019-02-12 10:27:25 +0800
commit0b5e69e1d5ec32aba660b256063ec0eac54174ac (patch)
tree2b1fdd56f95d033765a55694ceae7b1b1040becc
parent4d465c86d1f0f5f5b124a77cb873727f4484715c (diff)
MLK-15960-6: ARM64: dts: add power domain for audio clocks
The mclk_out clock is used as codec's mclk, so need to add its power domain to codec node. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi31
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi31
-rw-r--r--include/dt-bindings/soc/imx8_pd.h6
8 files changed, 71 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts
index cebcc87367d5..fbc4ec3ed230 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-mqs.dts
@@ -162,6 +162,7 @@
0x0000 /* 5:Default */
>;
amic-mono;
+ power-domains = <&pd_mclk_out0>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts
index 1af41352b243..63de79c13d18 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-spdif.dts
@@ -165,6 +165,7 @@
0x0000 /* 5:Default */
>;
amic-mono;
+ power-domains = <&pd_mclk_out0>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
index 43257d845ca7..5fa65afbcd17 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
@@ -525,6 +525,7 @@
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
reset-gpio = <&pca9557_a 2 1>;
+ power-domains = <&pd_mclk_out0>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index eef4da7d0ed7..c05546948132 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -621,6 +621,36 @@
#power-domain-cells = <0>;
power-domains =<&pd_audio>;
};
+ pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
+ reg = <SC_R_MCLK_OUT_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
+ reg = <SC_R_MCLK_OUT_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
+ reg = <SC_R_AUDIO_PLL_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
+ reg = <SC_R_AUDIO_PLL_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
+ reg = <SC_R_AUDIO_CLK_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
+ reg = <SC_R_AUDIO_CLK_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
};
pd_dma: PD_DMA {
@@ -2118,7 +2148,6 @@
acm: acm@59e00000 {
compatible = "nxp,imx8qm-acm";
reg = <0x0 0x59e00000 0x0 0x1D0000>;
- power-domains = <&pd_sai0>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts
index bcf8bf36a7b2..b441fcc44ce1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-wm8962.dts
@@ -98,6 +98,7 @@
0x0000 /* 5:Default */
>;
amic-mono;
+ power-domains = <&pd_mclk_out0>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
index d70ae79e39e1..1176cf7d77cf 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
@@ -386,6 +386,7 @@
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
reset-gpio = <&pca9557_a 2 1>;
+ power-domains = <&pd_mclk_out0>;
status = "okay";
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index a4ea4cfda248..0e6730b649f9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -437,6 +437,36 @@
#power-domain-cells = <0>;
power-domains =<&pd_audio>;
};
+ pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
+ reg = <SC_R_MCLK_OUT_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
+ reg = <SC_R_MCLK_OUT_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
+ reg = <SC_R_AUDIO_PLL_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
+ reg = <SC_R_AUDIO_PLL_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
+ reg = <SC_R_AUDIO_CLK_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
+ pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
+ reg = <SC_R_AUDIO_CLK_1>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_audio>;
+ };
};
pd_dma: PD_DMA {
@@ -1363,7 +1393,6 @@
acm: acm@59e00000 {
compatible = "nxp,imx8qm-acm";
reg = <0x0 0x59e00000 0x0 0x1D0000>;
- power-domains = <&pd_sai0>;
status = "disabled";
};
diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h
index 321f6a58b89c..6e241e09e090 100644
--- a/include/dt-bindings/soc/imx8_pd.h
+++ b/include/dt-bindings/soc/imx8_pd.h
@@ -143,6 +143,12 @@
#define PD_AUD_MQS_0 audio_mqs0
#define PD_AUD_HIFI audio_hifi
#define PD_AUD_OCRAM audio_ocram
+#define PD_AUD_MCLK_OUT_0 audio_mclkout0
+#define PD_AUD_MCLK_OUT_1 audio_mclkout1
+#define PD_AUD_AUDIO_PLL_0 audio_audiopll0
+#define PD_AUD_AUDIO_PLL_1 audio_audiopll1
+#define PD_AUD_AUDIO_CLK_0 audio_audioclk0
+#define PD_AUD_AUDIO_CLK_1 audio_audioclk1
#define PD_IMAGING imaging_power_domain
#define PD_IMAGING_JPEG_DEC imaging_jpeg_dec