MLK-16746 imx8mq: support m4

Support M4/A53 work together
1. add imx_src_is_m4_enabled
2. introduce a new dts dedicated for m4
3. add more pwm nodes
4. Since clk initialization is at very early stage, add m4 enabled check
   in the beginning of clk code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>

8 files changed, 121 insertions, 13 deletions

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a460eecdcd5c..443b25a647ed 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-evk.dtb \
 				 fsl-imx8mq-evk-od.dtb \
 				 fsl-imx8mq-evk-4k.dtb \
 				 fsl-imx8mq-evk-lcdif-dsi.dtb \
+				 fsl-imx8mq-evk-m4.dtb \
 				 fsl-imx8mq-evk-pcie1-m2.dtb
 
 always		:= $(dtb-y)
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-m4.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-m4.dts
new file mode 100644
index 000000000000..463ca18c9f54
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-m4.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8mq-evk.dts"
+
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		m4_reserved: m4@0x80000000 {
+			no-map;
+			reg = <0 0x80000000 0 0x1000000>;
+		};
+
+	};
+};
+
+&gpt1 {
+	status = "disabled";
+};
+
+&i2c2 {
+	status = "disabled";
+};
+
+&pwm4 {
+	status = "disabled";
+};
+
+&tmu {
+	status = "disabled";
+};
+
+&uart2 {
+	status = "disabled";
+};
+
+&wdog3{
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
index bcee1e3b74d0..653ed59c307e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
@@ -239,6 +239,17 @@
 		domain-name = "PCIE1_PD";
 	};
 
+	pwm1: pwm@30660000 {
+		compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x30660000 0x0 0x10000>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
+			 <&clk IMX8MQ_CLK_PWM1_ROOT>;
+		clock-names = "ipg", "per";
+		#pwm-cells = <2>;
+		status = "disabled";
+	};
+
 	pwm2: pwm@30670000 {
 		compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x30670000 0x0 0x10000>;
@@ -250,6 +261,28 @@
 		status = "disabled";
 	};
 
+	pwm3: pwm@30680000 {
+		compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x30680000 0x0 0x10000>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
+			 <&clk IMX8MQ_CLK_PWM3_ROOT>;
+		clock-names = "ipg", "per";
+		#pwm-cells = <2>;
+		status = "disabled";
+	};
+
+	pwm4: pwm@30690000 {
+		compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x30690000 0x0 0x10000>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
+			 <&clk IMX8MQ_CLK_PWM4_ROOT>;
+		clock-names = "ipg", "per";
+		#pwm-cells = <2>;
+		status = "disabled";
+	};
+
 	gpio1: gpio@30200000 {
 		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 		reg = <0x0 0x30200000 0x0 0x10000>;
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 69b844bdbe83..d163252cf3e8 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -19,6 +19,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/types.h>
+#include <soc/imx8/soc.h>
 
 #include "clk.h"
 
@@ -56,9 +57,6 @@ static const char *video2_pll2_out_sels[] = {"video2_pll2_div", "video2_pll1_ref
 static const char *imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
 					"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", };
 
-static const char *imx8mq_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",
-				       "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
-
 static const char *imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
 					"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", };
 
@@ -293,6 +291,8 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
 	void __iomem *base;
 	int i;
 
+	check_m4_enabled();
+
 	clks[IMX8MQ_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
 	clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(ccm_node, "ckil");
 	clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(ccm_node, "osc_25m");
@@ -426,18 +426,15 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
 	WARN_ON(!base);
 	/* CORE */
 	clks[IMX8MQ_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
-	clks[IMX8MQ_CLK_M4_SRC] = imx_clk_mux2("arm_m4_src", base + 0x8080, 24, 3, imx8mq_m4_sels, ARRAY_SIZE(imx8mq_m4_sels));
 	clks[IMX8MQ_CLK_VPU_SRC] = imx_clk_mux2("vpu_src", base + 0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels));
 	clks[IMX8MQ_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3,  imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels));
 	clks[IMX8MQ_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mq_gpu_shader_sels,  ARRAY_SIZE(imx8mq_gpu_shader_sels));
 	clks[IMX8MQ_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
-	clks[IMX8MQ_CLK_M4_CG] = imx_clk_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28);
 	clks[IMX8MQ_CLK_VPU_CG] = imx_clk_gate3("vpu_cg", "vpu_src", base + 0x8100, 28);
 	clks[IMX8MQ_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
 	clks[IMX8MQ_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
 
 	clks[IMX8MQ_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
-	clks[IMX8MQ_CLK_M4_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
 	clks[IMX8MQ_CLK_VPU_DIV] = imx_clk_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3);
 	clks[IMX8MQ_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
 	clks[IMX8MQ_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
index c3444abd72f3..a25b3b16da46 100644
--- a/drivers/soc/imx/soc-imx8.c
+++ b/drivers/soc/imx/soc-imx8.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <linux/arm-smccc.h>
 #include <linux/cpu.h>
 #include <linux/init.h>
 #include <linux/io.h>
@@ -26,6 +27,8 @@
 #include <soc/imx8/sc/sci.h>
 #include <soc/imx8/soc.h>
 #include <soc/imx/revision.h>
+#include <soc/imx/src.h>
+#include <soc/imx/fsl_sip.h>
 
 #define ANADIG_DIGPROG		0x6c
 
@@ -346,3 +349,24 @@ static int __init imx8_register_cpufreq(void)
 	return 0;
 }
 late_initcall(imx8_register_cpufreq);
+
+/* To indicate M4 enabled or not on i.MX8MQ */
+static bool m4_is_enabled;
+bool imx_src_is_m4_enabled(void)
+{
+	return m4_is_enabled;
+}
+
+int check_m4_enabled(void)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(FSL_SIP_SRC, FSL_SIP_SRC_M4_STARTED, 0,
+		      0, 0, 0, 0, 0, &res);
+	m4_is_enabled = !!res.a0;
+
+	if (m4_is_enabled)
+		printk("M4 is started\n");
+
+	return 0;
+}
diff --git a/include/soc/imx/fsl_sip.h b/include/soc/imx/fsl_sip.h
index 26481a0865ac..e4d02126e5f8 100644
--- a/include/soc/imx/fsl_sip.h
+++ b/include/soc/imx/fsl_sip.h
@@ -47,4 +47,9 @@
 #define SC_TIMER_WDOG_ACTION_COLD           2   /*!< Cold reset system */
 #define SC_TIMER_WDOG_ACTION_BOARD          3   /*!< Reset board */
 
+#define FSL_SIP_DDR_DVFS		0xc2000004
+
+#define FSL_SIP_SRC			0xc2000005
+#define FSL_SIP_SRC_M4_START		0x00
+#define FSL_SIP_SRC_M4_STARTED		0x01
 #endif
diff --git a/include/soc/imx/src.h b/include/soc/imx/src.h
index b4f8944ea696..c55c34cd2366 100644
--- a/include/soc/imx/src.h
+++ b/include/soc/imx/src.h
@@ -1,13 +1,6 @@
 #ifndef __SOC_IMX_SRC_H
 #define __SOC_IMX_SRC_H
 
-#ifndef CONFIG_ARM64
 bool imx_src_is_m4_enabled(void);
-#else
-static inline bool imx_src_is_m4_enabled(void)
-{
-	return 0;
-}
-#endif
 
 #endif /* __SOC_IMX_SRC_H */
diff --git a/include/soc/imx8/soc.h b/include/soc/imx8/soc.h
index 70c75fada62b..0d3fedc0f34c 100644
--- a/include/soc/imx8/soc.h
+++ b/include/soc/imx8/soc.h
@@ -27,4 +27,6 @@ bool cpu_is_imx8qxp(void);
 extern bool TKT340553_SW_WORKAROUND;
 unsigned int imx8_get_soc_revision(void);
 
+int check_m4_enabled(void);
+
 #endif