diff options
| author | Jinyoung Park <jinyoungp@nvidia.com> | 2012-04-25 20:07:16 +0900 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-05-01 14:13:56 -0700 |
| commit | 97bb37f1a9a9f255fea25d99ee2ad8a399d500b6 (patch) | |
| tree | d3606f4db7cb5bd9aa6ba1d4989a86eef8f15eea | |
| parent | bc18103a71dabc08fa26a287632e33f0c61b4a8e (diff) | |
mfd: max77663: Add FPWM and FSRADE clearing when initialization
If sd power rail is not configured to FORCED_PWM_MODE or
FSRADE_DISABLE, clear corresponding bits(FPWM and FSRADE)
when initialization.
Change-Id: I4e08329a430c6ccf7179b77cc7a283460ffaedd1
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/98715
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
| -rw-r--r-- | drivers/regulator/max77663-regulator.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/regulator/max77663-regulator.c b/drivers/regulator/max77663-regulator.c index dca8ece4c433..c9001c0a3e9f 100644 --- a/drivers/regulator/max77663-regulator.c +++ b/drivers/regulator/max77663-regulator.c @@ -704,15 +704,13 @@ skip_init_apply: val |= (SD_SR_100 << SD_SR_SHIFT); } - if (pdata->flags & SD_FORCED_PWM_MODE) { - mask |= SD_FPWM_MASK; + mask |= SD_FPWM_MASK; + if (pdata->flags & SD_FORCED_PWM_MODE) val |= SD_FPWM_MASK; - } - if (pdata->flags & SD_FSRADE_DISABLE) { - mask |= SD_FSRADE_MASK; + mask |= SD_FSRADE_MASK; + if (pdata->flags & SD_FSRADE_DISABLE) val |= SD_FSRADE_MASK; - } ret = max77663_regulator_cache_write(reg, reg->regs[CFG_REG].addr, mask, val, |