MLK-20060-5 dts: lpspi: add dma mode support

Add dma configurations in dts files, for imx7ulp and imx8qm.

There is no "edma0" node in fsl-imx8qm-mek(or lpddr4-arm2)-domu.dts.
lpspi0 node has been deleted in these dts files, so delete lpspi3 node.

Add edma0a and edma0d for lpspi0 and lpspi3, and enable lpspi0/3 for xen.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Acked-by: Fugang Duan <Fugang.duan@nxp.com>

7 files changed, 106 insertions, 6 deletions

diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
index 973f1b810c6e..366abe6fedcc 100644
--- a/arch/arm/boot/dts/imx7ulp-evk.dts
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -464,6 +464,7 @@
 &lpspi3 {
 	#address-cells = <1>;
 	#size-cells = <0>;
+	fsl,spi-num-chipselects = <1>;
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pinctrl_lpspi3>;
 	pinctrl-1 = <&pinctrl_lpspi3>;
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 0730ae7ce6cd..58d4062d38e5 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -304,6 +304,8 @@
 			assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
 			assigned-clock-rates = <48000000>;
+			dmas = <&edma0 0 26>, <&edma0 0 25>;
+			dma-names = "tx","rx";
 			status = "disabled";
 		};
 
@@ -317,6 +319,8 @@
 			assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC_BUS_CLK>;
 			assigned-clock-rates = <48000000>;
+			dmas = <&edma0 0 28>, <&edma0 0 27>;
+			dma-names = "tx","rx";
 			status = "disabled";
 		};
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
index 5325b715ac0e..38a8edec61b2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
@@ -1117,6 +1117,24 @@
 				reg = <SC_R_SPI_0>;
 				#power-domain-cells = <0>;
 				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dma0_chan0: PD_LPSPI0_RX {
+					reg = <SC_R_DMA_0_CH0>;
+					power-domains =<&pd_dma_lpspi0>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma0_chan1: PD_LPSPI0_TX {
+						reg = <SC_R_DMA_0_CH1>;
+						power-domains =<&pd_dma0_chan0>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+			};
+				};
 			};
 			pd_dma_lpspi1: PD_DMA_SPI_1 {
 				reg = <SC_R_SPI_1>;
@@ -1132,6 +1150,24 @@
 				reg = <SC_R_SPI_3>;
 				#power-domain-cells = <0>;
 				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dma0_chan6: PD_LPSPI3_RX {
+					reg = <SC_R_DMA_0_CH6>;
+					power-domains =<&pd_dma_lpspi3>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma0_chan7: PD_LPSPI3_TX {
+						reg = <SC_R_DMA_0_CH7>;
+						power-domains =<&pd_dma0_chan6>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
 			};
 			pd_dma_emvsim0: PD_DMA_EMVSIM_0 {
 				reg = <SC_R_EMVSIM_0>;
@@ -2980,7 +3016,9 @@
 		clock-names = "per", "ipg";
 		assigned-clocks = <&clk IMX8QM_SPI0_CLK>;
 		assigned-clock-rates = <20000000>;
-		power-domains = <&pd_dma_lpspi0>;
+		power-domains = <&pd_dma0_chan1>;
+		dma-names = "tx","rx";
+		dmas = <&edma0 1 0 0>, <&edma0 0 0 1>;
 		status = "disabled";
 	};
 
@@ -2994,7 +3032,9 @@
 		clock-names = "per", "ipg";
 		assigned-clocks = <&clk IMX8QM_SPI3_CLK>;
 		assigned-clock-rates = <60000000>;
-		power-domains = <&pd_dma_lpspi3>;
+		power-domains = <&pd_dma0_chan7>;
+		dma-names = "tx","rx";
+		dmas = <&edma0 7 0 0>, <&edma0 6 0 1>;
 		status = "disabled";
 	};
 
@@ -3129,7 +3169,11 @@
 
 	edma0: dma-controller@5a1f0000 {
 		compatible = "fsl,imx8qm-edma";
-		reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
+		reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */
+		      <0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */
+		      <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */
+		      <0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */
+		      <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
 		      <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
 		      <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
 		      <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */
@@ -3140,8 +3184,12 @@
 		      <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */
 		      <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */
 		#dma-cells = <3>;
-		dma-channels = <10>;
-		interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+		dma-channels = <14>;
+		interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
@@ -3151,7 +3199,9 @@
 			     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx",
+		interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx",
+				  "edma0-chan6-rx", "edma0-chan7-tx",
+				  "edma0-chan12-rx", "edma0-chan13-tx",
 				  "edma0-chan14-rx", "edma0-chan15-tx",
 				  "edma0-chan16-rx", "edma0-chan17-tx",
 				  "edma0-chan18-rx", "edma0-chan19-tx",
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts
index 0c6e5156bd38..13ecc444bca9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts
@@ -377,6 +377,7 @@
 /delete-node/ &irqsteer_csi1;
 /delete-node/ &i2c0_mipi_csi1;
 /delete-node/ &lpspi0;
+/delete-node/ &lpspi3;
 /delete-node/ &lpuart0;
 
 &lpuart1 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts
index 271d24e0c4a0..556c8be14b17 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts
@@ -538,6 +538,7 @@
 /delete-node/ &irqsteer_csi1;
 /delete-node/ &i2c0_mipi_csi1;
 /delete-node/ &lpspi0;
+/delete-node/ &lpspi3;
 /delete-node/ &lpuart0;
 
 &lpuart1 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts
index a8a4f8b6c916..23a31dc775ba 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts
@@ -690,6 +690,7 @@
 /delete-node/ &irqsteer_csi1;
 /delete-node/ &i2c0_mipi_csi1;
 /delete-node/ &lpspi0;
+/delete-node/ &lpspi3;
 /delete-node/ &lpuart0;
 
 &lpuart1 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi
index f3b0d736c97a..5b11bb8337b8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi
@@ -20,6 +20,38 @@
 
 	/delete-node/ wu;
 
+	/*
+	 * This is just to avoid renaming all other edma0 nodes, so choose
+	 * edma0a and edma0d here.
+	 */
+	edma0a: dma-controller0@5a200000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */
+		      <0x0 0x5a210000 0x0 0x10000>; /* channel1 LPSPI0 tx */
+		#dma-cells = <3>;
+		dma-channels = <2>;
+		interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx";
+		fsl,sc_rsrc_id = <SC_R_DMA_0_CH0>,
+				 <SC_R_DMA_0_CH1>;
+		status = "okay";
+	};
+
+	edma0d: dma-controller0@5a260000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */
+		      <0x0 0x5a270000 0x0 0x10000>; /* channel7 LPSPI3 tx */
+		#dma-cells = <3>;
+		dma-channels = <2>;
+		interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan6-rx", "edma0-chan7-tx";
+		fsl,sc_rsrc_id = <SC_R_DMA_0_CH6>,
+				 <SC_R_DMA_0_CH7>;
+		status = "okay";
+	};
+
 	edma00: dma-controller0@5a2c0000 {
 		compatible = "fsl,imx8qm-edma";
 		reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
@@ -406,6 +438,16 @@
 	interrupt-parent = <&gic>;
 };
 
+&lpspi0 {
+	interrupt-parent = <&gic>;
+	dmas = <&edma0a 1 0 0>, <&edma0a 0 0 1>;
+};
+
+&lpspi3 {
+	interrupt-parent = <&gic>;
+	dmas = <&edma0d 7 0 0>, <&edma0d 6 0 1>;
+};
+
 &lpuart0 {
 	interrupt-parent = <&gic>;
 };