diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-03-26 14:13:43 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-03-26 15:59:21 +0800 |
| commit | c2937fd8fe144519d6461d396ed6e9066749ba21 (patch) | |
| tree | d4f143a22f3210370d8aaf48d5833400b4c269c4 | |
| parent | 82a6695ed109efa89307b4b0b5a53ba12f792b29 (diff) | |
MLK-23681 arm64: dts: imx: enable pcieb on 8qm mek baseboard
Based on imx_4.1x kernel, enable the PCIEB on i.MX8QM MEK baseboard.
Regarding to the base board HW limitation(two Disable#) are not
connected. Only the standard PCIe EP device is supported on PCIEB port.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
(cherry picked from commit d0331d84e5a14d6e2520d04540d1e893d75bd678)
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi index 4c2c29695644..8634b5d1f30a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi @@ -466,6 +466,14 @@ >; }; + pinctrl_pcieb: pciebgrp { + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + pinctrl_sim0: sim0grp { fsl,pins = < SC_P_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 @@ -1138,6 +1146,15 @@ status = "okay"; }; +&pcieb { + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &intmux_cm40 { status = "okay"; }; |