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authorAnson Huang <Anson.Huang@nxp.com>2017-07-19 21:09:46 +0800
committerJason Liu <jason.hui.liu@nxp.com>2019-02-12 10:27:33 +0800
commitf260372d7a61994615236d85bfd714ec34af2352 (patch)
tree86ed7657073b163650d272863865b23f86cb1cc5
parenta88e4cda511267e398b2ff311121da9aa4c92af3 (diff)
MLK-16030-2 soc: imx: gpc: add power domain names
Add power domain names for i.MX8MQ, currently only 11 power domains support runtime ON/OFF. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
-rw-r--r--drivers/soc/imx/gpc-psci.c16
-rw-r--r--include/soc/imx/fsl_sip.h12
2 files changed, 27 insertions, 1 deletions
diff --git a/drivers/soc/imx/gpc-psci.c b/drivers/soc/imx/gpc-psci.c
index 7b3ffa8f9662..1445b1429197 100644
--- a/drivers/soc/imx/gpc-psci.c
+++ b/drivers/soc/imx/gpc-psci.c
@@ -200,6 +200,20 @@ static int imx_gpc_pd_power_off(struct generic_pm_domain *domain)
return 0;
};
+static const char * const imx8mq_powergates[] = {
+ [IMX8MQ_PD_MIPI] = "mipi",
+ [IMX8MQ_PD_PCIE1] = "pcie1",
+ [IMX8MQ_PD_OTG1] = "otg1",
+ [IMX8MQ_PD_OTG2] = "otg2",
+ [IMX8MQ_PD_GPU] = "gpu",
+ [IMX8MQ_PD_VPU] = "vpu",
+ [IMX8MQ_PD_HDMI] = "hdmi",
+ [IMX8MQ_PD_DISP] = "disp",
+ [IMX8MQ_PD_MIPI_CSI1] = "mipi_csi1",
+ [IMX8MQ_PD_MIPI_CSI2] = "mipi_csi2",
+ [IMX8MQ_PD_PCIE2] = "pcie2",
+};
+
static int imx_gpc_pm_domain_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -236,7 +250,7 @@ static int imx_gpc_pm_domain_probe(struct platform_device *pdev)
for (i = 0; i < num_domains; i++, imx_pm_domain++) {
domains[i] = &imx_pm_domain->pd;
imx_pm_domain->gpc_domain_id = i;
- sprintf(imx_pm_domain->name, "%s.%d", np->name, i);
+ strcpy(imx_pm_domain->name, imx8mq_powergates[i]);
imx_pm_domain->pd.name = imx_pm_domain->name;
imx_pm_domain->pd.power_off = imx_gpc_pd_power_off;
imx_pm_domain->pd.power_on = imx_gpc_pd_power_on;
diff --git a/include/soc/imx/fsl_sip.h b/include/soc/imx/fsl_sip.h
index d865daf5094a..c3867a2688c2 100644
--- a/include/soc/imx/fsl_sip.h
+++ b/include/soc/imx/fsl_sip.h
@@ -16,4 +16,16 @@
#define FSL_SIP_CONFIG_GPC_SET_WAKE 0x02
#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03
+#define IMX8MQ_PD_MIPI 0
+#define IMX8MQ_PD_PCIE1 1
+#define IMX8MQ_PD_OTG1 2
+#define IMX8MQ_PD_OTG2 3
+#define IMX8MQ_PD_GPU 4
+#define IMX8MQ_PD_VPU 5
+#define IMX8MQ_PD_HDMI 6
+#define IMX8MQ_PD_DISP 7
+#define IMX8MQ_PD_MIPI_CSI1 8
+#define IMX8MQ_PD_MIPI_CSI2 9
+#define IMX8MQ_PD_PCIE2 10
+
#endif