diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-02-19 12:56:04 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-12-09 23:11:23 +0100 |
| commit | df95d1fa8f825cf74619f3bf3d24bc654e58aac4 (patch) | |
| tree | 7c6a64756dd66a18426c03caaf083300c84acaa8 | |
| parent | f0f7a33f4c1fbed4c5d1bf2938e22884309bd239 (diff) | |
ARM: imx: mach-imx7d: put external ethernet clock in error case
Exit early in case General-Purpose Registers are missing. This makes
sure that clock is always freed properly (clk_put).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | arch/arm/mach-imx/mach-imx7d.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index 36d5954fc353..d9441898e756 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -98,6 +98,12 @@ static void __init imx7d_enet_clk_sel(void) struct clk *enet_out_clk; struct regmap *gpr; + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); + if (IS_ERR(gpr)) { + pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); + return; + } + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-fec"); if (!np) { pr_warn("%s: failed to find fec node\n", __func__); @@ -106,25 +112,19 @@ static void __init imx7d_enet_clk_sel(void) enet_out_clk = of_clk_get_by_name(np, "enet_out"); - gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); - - if (!IS_ERR(gpr)) { - if (IS_ERR(enet_out_clk)) { - pr_info("%s: failed to get enet_out clock, assuming ext. clock source\n", __func__); - /* use external clock for PHY */ - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK); - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); - } else { - pr_info("%s: found enet_out clock, assuming internal clock source\n", __func__); - /* use internal clock generation and output it to PHY */ - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, IMX7D_GPR1_ENET1_CLK_DIR_MASK); - clk_put(enet_out_clk); - - } + if (IS_ERR(enet_out_clk)) { + pr_info("%s: failed to get enet_out clock, assuming ext. clock source\n", __func__); + /* use external clock for PHY */ + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK); + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); } else { - pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); + pr_info("%s: found enet_out clock, assuming internal clock source\n", __func__); + /* use internal clock generation and output it to PHY */ + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, IMX7D_GPR1_ENET1_CLK_DIR_MASK); + clk_put(enet_out_clk); } + of_node_put(np); } |